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authorMatt DeVillier <matt.devillier@gmail.com>2018-02-19 17:35:55 -0600
committerMartin Roth <martinroth@google.com>2018-03-01 16:10:25 +0000
commit0f49bbceef3ee4d0755c5784c3dd647528b3c7bc (patch)
treed8a0a74920d20a3ba3fbe134496036458dd42259 /src/soc/intel/broadwell/chip.c
parent81a6f109bab8f58984603fbd534e2548be290480 (diff)
downloadcoreboot-0f49bbceef3ee4d0755c5784c3dd647528b3c7bc.tar.xz
soc/intel/broadwell: Generate ACPI DMAR table
If the SoC is VT-d capable, write an ACPI DMAR table. The entry for the GFXVTBAR is only generated if the IGD is enabled. Change-Id: Id7c899954f1bae9d2b48532ca5ee271944f0c5f6 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/23821 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Youness Alaoui <snifikino@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel/broadwell/chip.c')
-rw-r--r--src/soc/intel/broadwell/chip.c12
1 files changed, 8 insertions, 4 deletions
diff --git a/src/soc/intel/broadwell/chip.c b/src/soc/intel/broadwell/chip.c
index 8176c8ecda..c282c6b14a 100644
--- a/src/soc/intel/broadwell/chip.c
+++ b/src/soc/intel/broadwell/chip.c
@@ -16,6 +16,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
+#include <soc/acpi.h>
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
#include <soc/intel/broadwell/chip.h>
@@ -26,10 +27,13 @@ static void pci_domain_set_resources(device_t dev)
}
static struct device_operations pci_domain_ops = {
- .read_resources = &pci_domain_read_resources,
- .set_resources = &pci_domain_set_resources,
- .scan_bus = &pci_domain_scan_bus,
- .ops_pci_bus = &pci_bus_default_ops,
+ .read_resources = &pci_domain_read_resources,
+ .set_resources = &pci_domain_set_resources,
+ .scan_bus = &pci_domain_scan_bus,
+ .ops_pci_bus = &pci_bus_default_ops,
+#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+ .write_acpi_tables = &northbridge_write_acpi_tables,
+#endif
};
static struct device_operations cpu_bus_ops = {