broadwell: Misc updates from 2.1.0 ref code

- ADSP IRQ should be exclusive
- HDA should write reg 0x43 even if disabled
- A few clock gating tweaks based on ref code changes
- Move SATA clock gating to sata.c where SIR changes are done
- Add support for enabling Deep SX in AC/DC modes
- CLKREQ VR Idle for enabled PCIE ports

BUG=chrome-os-partner:28234
BRANCH=None
TEST=build and boot on samus

Original-Change-Id: Icece58e32b7a5d2b359debd5516a230cae3fd48c
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/211611
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit c0e22ba043ed96bdddca4989b2f29d0e989f6fef)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: If5f5e1666aa9660e31305ee6369f2febf6757b99
Reviewed-on: http://review.coreboot.org/8952
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>

1 files changed, 4 insertions, 0 deletions

diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h
index e433483198..005ab36551 100644
--- a/src/soc/intel/broadwell/chip.h
+++ b/src/soc/intel/broadwell/chip.h
@@ -129,6 +129,10 @@ struct soc_intel_broadwell_config {
 	/* Enable S0iX support */
 	int s0ix_enable;
 
+	/* Deep SX enable */
+	int deep_sx_enable_ac;
+	int deep_sx_enable_dc;
+
 	/* TCC activation offset */
 	int tcc_offset;
 };