broadwell: add new intel SOC

broadwell: Import files from haswell/lynxpoint into soc/broadwell
Reviewed-on: https://chromium-review.googlesource.com/198425
(cherry picked from commit 178400e5709d676dd41e6a75df06faa829e0e3af)

broadwell: Unify and clean up license
Reviewed-on: https://chromium-review.googlesource.com/198426
(cherry picked from commit 30d3c25a0abc76be68477c39a654b95a5975f55d)

broadwell: pch.h: split PM into new header
Reviewed-on: https://chromium-review.googlesource.com/198427
(cherry picked from commit 97a8d0b051f476d0edc06301f57326a718df1373)

broadwell: pch.h: split RCBA into new header
Reviewed-on: https://chromium-review.googlesource.com/198428
(cherry picked from commit fa217361b28fdb8d3a3e85f070dfaf13c0d48135)

broadwell: pch.h: split SATA into new header
Reviewed-on: https://chromium-review.googlesource.com/198429
(cherry picked from commit bf8795ca92f9f0467e7869c701038abb4529ac71)

broadwell: pch.h: split SPI into new header
Reviewed-on: https://chromium-review.googlesource.com/198550
(cherry picked from commit 099af14676a2654ca3e24e66d7b9f0b4ab13cd14)

broadwell: pch.h: split SerialIO into new header
Reviewed-on: https://chromium-review.googlesource.com/198551
(cherry picked from commit 4f3c028686aed78fb07b8792dcf46aebd2268ea6)

broadwell: pch.h: split LPC into new header
Reviewed-on: https://chromium-review.googlesource.com/198552
(cherry picked from commit 10bad5bbb6739c0277fd5330d26a89d60fd5c102)

broadwell: pch.h: split GPIO into new header and clean up
Reviewed-on: https://chromium-review.googlesource.com/198553
(cherry picked from commit 9c97532460562215b78e10b011a29e092a07f3e5)

broadwell: pch.h: split USB into new headers
Reviewed-on: https://chromium-review.googlesource.com/198554
(cherry picked from commit 86ef1a45a2e5f307467b3be48e377569f37b3068)

broadwell: Split IOBP into separate files
Reviewed-on: https://chromium-review.googlesource.com/198734
(cherry picked from commit f93b8bda71728f1383937ad675d2d5fb5a927600)

broadwell: smbus: Extract common code and split header
Reviewed-on: https://chromium-review.googlesource.com/198735
(cherry picked from commit 8052030a9d6b22e8a19938fa9b93e90d08f0057d)

broadwell: Create iomap.h header with platform base addresses
Reviewed-on: https://chromium-review.googlesource.com/198736
(cherry picked from commit b35947d070b28871637dfe2b930a9f2be80958ee)

broadwell: Add header for platform PCI devices
Reviewed-on: https://chromium-review.googlesource.com/198737
(cherry picked from commit 6ac4e56db6e489bb9eaf91a0c3c543399f691500)

broadwell: Split SMM related defines/prototypes to new header
Reviewed-on: https://chromium-review.googlesource.com/198738
(cherry picked from commit 2a2595067077cd918bfd48cad79a684b8e1ff0f4)

broadwell: cpu.h: Split MSR defines to separate header
Reviewed-on: https://chromium-review.googlesource.com/198739
(cherry picked from commit 01148cd2c9edd97cd0c8ef3cfed58bc8c33eb805)

broadwell: Create romstage header file
Reviewed-on: https://chromium-review.googlesource.com/198740
(cherry picked from commit 31c91e811b9e07e7bcba6b9f8f5720a31322eb21)

broadwell: Create ram stage header file
Reviewed-on: https://chromium-review.googlesource.com/198741
(cherry picked from commit 93dde85f98d43d4a1886b59004d1bab4924ad621)

broadwell: Add reference code data interface
Reviewed-on: https://chromium-review.googlesource.com/198743
(cherry picked from commit 9059b8e2308892a48c838c3099404c9cf450df95)

broadwell: Clean up ACPI NVS region
Reviewed-on: https://chromium-review.googlesource.com/198897
(cherry picked from commit d83cc82c36661556eb1e2e437b7ac51d5b8e4a14)

broadwell: Move CTDP ACPI methods to new file
Reviewed-on: https://chromium-review.googlesource.com/198898
(cherry picked from commit fc1e711290df304d18c558d697eea8a5e57061b2)

broadwell: Split EHCI and XHCI ACPI devices
Reviewed-on: https://chromium-review.googlesource.com/198899
(cherry picked from commit 26f437b27e00dbd5c92ea22e76404633a62fb7ca)

broadwell: ACPI: Clean up SerialIO ACPI code
Reviewed-on: https://chromium-review.googlesource.com/198910
(cherry picked from commit ea3cd39566c1bb2ead463a6253b6204a62545d35)

broadwell: ACPI: Remove special handling of LPT-LP chipset
Reviewed-on: https://chromium-review.googlesource.com/198911
(cherry picked from commit 2c54df159bf6759c8f866628e83541de6f4e28f6)

broadwell: ACPI: Clean up use of base address defines
Reviewed-on: https://chromium-review.googlesource.com/198912
(cherry picked from commit 34e4788955bceff01631fd0b4dbf0aa24cf56b75)

broadwell: ACPI: Clean up and fix formatting
Reviewed-on: https://chromium-review.googlesource.com/198913
(cherry picked from commit bc0f7c6d2f95681eb987bb6ff6baf2d16cc77050)

broadwell: Add header for ACPI defines and prototypes
Reviewed-on: https://chromium-review.googlesource.com/198914
(cherry picked from commit 9951e7931942d2921f92f6e094b1cc32c190eab9)

broadwell: Add reset_system function and header
Reviewed-on: https://chromium-review.googlesource.com/198915
(cherry picked from commit 6d1efb94bd39bcd6f7e3e0de2f3299a384b109ef)

broadwell: Move PCODE MMIO defines to systemagent.h
Reviewed-on: https://chromium-review.googlesource.com/198916
(cherry picked from commit abb5f87e548fbde3a08e14a18714b4e4391c955f)

broadwell: Unify chip.h and add chip.c
Reviewed-on: https://chromium-review.googlesource.com/198917
(cherry picked from commit a9c2d7ff3afa1e2a10be85ccc72b7db0f2aaafe1)

broadwell: Rename HASWELL_BCLK to CPU_BCLK
Reviewed-on: https://chromium-review.googlesource.com/198918
(cherry picked from commit 65ac1a07abaf14eb42fec6c5df67d2d3688ad5a1)

broadwell: Clean up broadwell/cpu.h
Reviewed-on: https://chromium-review.googlesource.com/198919
(cherry picked from commit 17353803babc8ace279e105c012130678226144e)

broadwell: Clean up broadwell/systemagent.h
Reviewed-on: https://chromium-review.googlesource.com/198920
(cherry picked from commit 49d7a023f3ff04a65d16622aa9b2fa6004b693ae)

broadwell: Clean up broadwell/pch.h
Reviewed-on: https://chromium-review.googlesource.com/198921
(cherry picked from commit 17da652b4408a91fcfea99dd35fe9f9e1bdcf03b)

broadwell: Clean up management engine driver
Reviewed-on: https://chromium-review.googlesource.com/198922
(cherry picked from commit 4fce5fbb56dc4f31b77e5ada05463c043ad5be72)

broadwell: Add common CPUID and PCI Device ID defines
Reviewed-on: https://chromium-review.googlesource.com/198923
(cherry picked from commit c6bf20309f33168ea2cc4634cbda5ec242824ba8)

broadwell: Clean up and expand report_platform
Reviewed-on: https://chromium-review.googlesource.com/198924
(cherry picked from commit 5082d4824db149e867a2cd8be34c932b03754022)

broadwell: Clean up the bootblock code
Reviewed-on: https://chromium-review.googlesource.com/198925
(cherry picked from commit ba0206ab76fe0b6834a14dc57f400d139094623c)

broadwell: Clean up ramstage device and driver operations
Reviewed-on: https://chromium-review.googlesource.com/199180
(cherry picked from commit d8fc9daf129738713a5059286b7ead004f3b7569)

broadwell: Clean up XHCI and EHCI ramstage drivers
Reviewed-on: https://chromium-review.googlesource.com/199181
(cherry picked from commit d355247333a828a146ce7cf9b92a63da74119c1d)

broadwell: Clean up gpio handling code
Reviewed-on: https://chromium-review.googlesource.com/199182
(cherry picked from commit d62cef1970fe75f8166315016b3d8415cddcab20)

broadwell: Clean up the PCH generic code
Reviewed-on: https://chromium-review.googlesource.com/199183
(cherry picked from commit 3b93b3ea79965d5ac831bf9015e49330f157b0ff)

broadwell: Move get_top_of_ram() and cbmem_top() to memmap.c
Reviewed-on: https://chromium-review.googlesource.com/199184
(cherry picked from commit 68955ba4ff8b49ff466d7badaa934bd143026ba7)

broadwell: Clean up pmutil.c
Reviewed-on: https://chromium-review.googlesource.com/199185
(cherry picked from commit b6fb672ae879e17422f7449f70c3669055096f84)

broadwell: pmutil: Add new acpi_sci_irq() function
Reviewed-on: https://chromium-review.googlesource.com/199186
(cherry picked from commit 80ad8bb9bdc75f180e667861fed42a3844226bc5)

broadwell: Clean up HDA ramstage driver
Reviewed-on: https://chromium-review.googlesource.com/199187
(cherry picked from commit b4962acd706eaa66c1c3ef4d22eba313642fbb2d)

broadwell: Clean up cache_as_ram assembly
Reviewed-on: https://chromium-review.googlesource.com/199188
(cherry picked from commit 8a457b82610b604ae7f69e2500815ce411c2d02d)

broadwell: romstage: Separate stack helper functions
Reviewed-on: https://chromium-review.googlesource.com/199189
(cherry picked from commit c220383c90466fc2dbf4b6107679b08ecb4aadad)

broadwell: Add function to read WPSR from SPI
Reviewed-on: https://chromium-review.googlesource.com/199190
(cherry picked from commit 935404da1157d606b913eff6c2635ae898e9980a)

broadwell: Clean up SMBUS code in romstage and ramstage
Reviewed-on: https://chromium-review.googlesource.com/199191
(cherry picked from commit 6ae9d93c1a6f14da6429a4e5b01619c9ccaefdaa)

broadwell: SPI: Clean up romstage and ramstage code
Reviewed-on: https://chromium-review.googlesource.com/199192
(cherry picked from commit 28ffd71a416aee2ab54bc5d782cfeef31d4d30bf)

broadwell: Clean up PCIe root port ramstage driver
Reviewed-on: https://chromium-review.googlesource.com/199193
(cherry picked from commit 781f3a1b72c72f0bb05f5524edec471ad13ec90e)

broadwell: Clean up minihd ramstage driver
Reviewed-on: https://chromium-review.googlesource.com/199194
(cherry picked from commit a52d275e41fdcbf9895d07350725609d9be1ff0e)

broadwell: Update romstage main to follow baytrail format
Reviewed-on: https://chromium-review.googlesource.com/199361
(cherry picked from commit 0678c739af84c871922ffba5594132b25e471ddd)

broadwell: Add CPU set_max_freq function for romstage
Reviewed-on: https://chromium-review.googlesource.com/199362
(cherry picked from commit 68b0122472af27f38502d42a8a6c80678ddbbba6)

broadwell: romstage: Add chipset_power_state implementation
Reviewed-on: https://chromium-review.googlesource.com/199363
(cherry picked from commit 761cec3b6bb9bde579c3214f3f1196f65700757c)

broadwell: romstage: Convert systemagent init to reg_script
Reviewed-on: https://chromium-review.googlesource.com/199364
(cherry picked from commit c2ea2d3a0c7555a353fb9a1d4a63e773ac8961b2)

broadwell: romstage: Convert pch init to reg_script
Reviewed-on: https://chromium-review.googlesource.com/199365
(cherry picked from commit 4383de5846e97ca5aee6dd210459d8dba0af981c)

broadwell: elog: Use chipset_power_state for events
Reviewed-on: https://chromium-review.googlesource.com/199366
(cherry picked from commit 0ef5961ebe3a7037d5fbe361fbc70a87ac2edad9)

broadwell: Clean up SATA ramstage driver
Reviewed-on: https://chromium-review.googlesource.com/199367
(cherry picked from commit ffa5743f74551bd48aa7e5445ce7cd9dc7b07ce8)

broadwell: Update ramstage graphics driver to support broadwell
Reviewed-on: https://chromium-review.googlesource.com/199368
(cherry picked from commit bb01deb8bbed56f15e1143504e4cf012ecf5a281)

broadwell: Update raminit to follow baytrail layout
Reviewed-on: https://chromium-review.googlesource.com/199369
(cherry picked from commit 3f25c23dc58f85d2521916cd6edbe9deeeb8d523)

broadwell: Update and unify the finalize steps
Reviewed-on: https://chromium-review.googlesource.com/199390
(cherry picked from commit ddc4c116b42d38dfdfc45ef4388fbfab32ca48fa)

broadwell: Clean up SMM code
Reviewed-on: https://chromium-review.googlesource.com/199391
(cherry picked from commit 8295e56c9b643fd4b9267d70b5efd0cf94dd67dd)

broadwell: Clean up LPC ramstage driver
Reviewed-on: https://chromium-review.googlesource.com/199392
(cherry picked from commit 28326aeaaf304c9262866588d91b79b37d1d9a2e)

broadwell: Clean up systemagent ramstage driver
Reviewed-on: https://chromium-review.googlesource.com/199393
(cherry picked from commit 749988fff07eab8d2c9ebc731e3ed9e427b3f7b3)

broadwell: Move C-state configuration information to acpi.c
Reviewed-on: https://chromium-review.googlesource.com/199394
(cherry picked from commit 198a3cd5cbd009be406298cbb53163f075fe9990)

broadwell: Clean up CPU ramstage driver
Reviewed-on: https://chromium-review.googlesource.com/199395
(cherry picked from commit 8159689bba479bab6fd2e949e3e1c3f817088969)

broadwell: Do not reserve SMM relocation region
Reviewed-on: https://chromium-review.googlesource.com/199402
(cherry picked from commit e2ab52340e3d3a97a3f8dbdad8fac9f7769d1b4c)

broadwell: Add an early ramstage driver
Reviewed-on: https://chromium-review.googlesource.com/199403
(cherry picked from commit c7a8c867101b49a7f9f17ec1a8777a8db145f3e3)

broadwell: Support for second reference code binary
Reviewed-on: https://chromium-review.googlesource.com/199404
(cherry picked from commit abb99b36e97c4f739b23abed6146fea370bbbec2)

broadwell: Clean up serialio init code
Reviewed-on: https://chromium-review.googlesource.com/199405
(cherry picked from commit e09a1f8520a7b72451a1e2068b200f7c5451f489)

broadwell: acpi: Add function to fill out FADT
Reviewed-on: https://chromium-review.googlesource.com/199406
(cherry picked from commit 7e58f43e46d4382cf4541057f81fe6be3e4d6e74)

broadwell: Update C-state table creation
Reviewed-on: https://chromium-review.googlesource.com/199407
(cherry picked from commit 68b1f70e32e1d0c6fc4332dce402ad78334e0063)

broadwell: acpi: Clean up acpi table creation code
Reviewed-on: https://chromium-review.googlesource.com/199408
(cherry picked from commit 49088b312b159bb17a9330eda6a88d6f324ea146)

broadwell: acpi: Add ACPI table create helper functions
Reviewed-on: https://chromium-review.googlesource.com/199409
(cherry picked from commit 344c3c511d0341457525ef4d6eb70201404fc62c)

broadwell: Add soc/intel/broadwell Makefiles
Reviewed-on: https://chromium-review.googlesource.com/199410
(cherry picked from commit ea8f97738eadd3b0b6a642754df7a7d22e547ffc)

broadwell: Add Kconfig for broadwell soc
Reviewed-on: https://chromium-review.googlesource.com/199411
(cherry picked from commit 8c99038a5c20812497619134c66d45bc4f21c8fe)

Squashed 78 commits for broadwell that form a solid code base.

Change-Id: I365ca9a45978b5e0cc5237f884e20a44f62a0e63
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6964
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>

1 files changed, 558 insertions, 0 deletions

diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c
new file mode 100644
index 0000000000..8235b3f3df
--- /dev/null
+++ b/src/soc/intel/broadwell/igd.c
@@ -0,0 +1,558 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <delay.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <stdlib.h>
+#include <string.h>
+#include <reg_script.h>
+#include <drivers/intel/gma/i915_reg.h>
+#include <broadwell/cpu.h>
+#include <broadwell/ramstage.h>
+#include <broadwell/systemagent.h>
+#include <chip.h>
+
+#define GT_RETRY 		1000
+#define GT_CDCLK_337		0
+#define GT_CDCLK_450		1
+#define GT_CDCLK_540		2
+#define GT_CDCLK_675		3
+
+struct reg_script haswell_early_init_script[] = {
+	/* Enable Force Wake */
+	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa180, 0x00000020),
+	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010001),
+	REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x130044, 1, 1, GT_RETRY),
+
+	/* Enable Counters */
+	REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa248, 0x00000016),
+
+	/* GFXPAUSE settings */
+	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa000, 0x00070020),
+
+	/* ECO Settings */
+	REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0xa180, 0xff3fffff, 0x15000000),
+
+	/* Enable DOP Clock Gating */
+	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9424, 0x000003fd),
+
+	/* Enable Unit Level Clock Gating */
+	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9400, 0x00000080),
+	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9404, 0x40401000),
+	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9408, 0x00000000),
+	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x940c, 0x02000001),
+
+	/*
+	 * RC6 Settings
+	 */
+
+	/* Wake Rate Limits */
+	REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa090, 0x00000000),
+	REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa098, 0x03e80000),
+	REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa09c, 0x00280000),
+	REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa0a8, 0x0001e848),
+	REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa0ac, 0x00000019),
+
+	/* Render/Video/Blitter Idle Max Count */
+	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x02054, 0x0000000a),
+	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x12054, 0x0000000a),
+	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x22054, 0x0000000a),
+	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1a054, 0x0000000a),
+
+	/* RC Sleep / RCx Thresholds */
+	REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa0b0, 0x00000000),
+	REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa0b4, 0x000003e8),
+	REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa0b8, 0x0000c350),
+
+	/* RP Settings */
+	REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa010, 0x000f4240),
+	REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa014, 0x12060000),
+	REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa02c, 0x0000e808),
+	REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa030, 0x0003bd08),
+	REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa068, 0x000101d0),
+	REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa06c, 0x00055730),
+	REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa070, 0x0000000a),
+
+	/* RP Control */
+	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa024, 0x00000b92),
+
+	/* HW RC6 Control */
+	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa090, 0x88040000),
+
+	/* Video Frequency Request */
+	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa00c, 0x08000000),
+
+	/* Set RC6 VIDs */
+	REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GT_RETRY),
+	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138128, 0),
+	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138124, 0x80000004),
+	REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GT_RETRY),
+
+	/* Enable PM Interrupts */
+	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x4402c, 0x03000076),
+
+	/* Enable RC6 in idle */
+	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa094, 0x00040000),
+
+	REG_SCRIPT_END
+};
+
+static const struct reg_script haswell_late_init_script[] = {
+	/* Lock settings */
+	REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a248, (1 << 31)),
+	REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a004, (1 << 4)),
+	REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a080, (1 << 2)),
+	REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a180, (1 << 31)),
+
+	/* Disable Force Wake */
+	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010000),
+	REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x130044, 1, 0, GT_RETRY),
+	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00000001),
+
+	/* Enable power well for DP and Audio */
+	REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x45400, (1 << 31)),
+	REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x45400,
+		       (1 << 30), (1 << 30), GT_RETRY),
+
+	REG_SCRIPT_END
+};
+
+static const struct reg_script broadwell_early_init_script[] = {
+	/* Enable Force Wake */
+	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010001),
+	REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x130044, 1, 1, GT_RETRY),
+
+	/* Enable push bus metric control and shift */
+	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa248, 0x00000004),
+	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa250, 0x000000ff),
+	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa25c, 0x00000010),
+
+	/* GFXPAUSE settings */
+	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa000, 0x00030020),
+
+	/* ECO Settings */
+	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa180, 0x45200000),
+
+	/* Enable DOP Clock Gating */
+	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9424, 0x000000fd),
+
+	/* Enable Unit Level Clock Gating */
+	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9400, 0x00000000),
+	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9404, 0x40401000),
+	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9408, 0x00000000),
+	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x940c, 0x02000001),
+	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1a054, 0x0000000a),
+
+	/* Video Frequency Request */
+	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa00c, 0x08000000),
+
+	/*
+	 * RC6 Settings
+	 */
+
+	/* Wake Rate Limits */
+	REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x0a090, 0, 0),
+	REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a098, 0x03e80000),
+	REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a09c, 0x00280000),
+	REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a0a8, 0x0001e848),
+	REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a0ac, 0x00000019),
+
+	/* Render/Video/Blitter Idle Max Count */
+	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x02054, 0x0000000a),
+	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x12054, 0x0000000a),
+	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x22054, 0x0000000a),
+
+	/* RC Sleep / RCx Thresholds */
+	REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a0b0, 0x00000000),
+	REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a0b8, 0x00000271),
+
+	/* RP Settings */
+	REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a010, 0x000f4240),
+	REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a014, 0x12060000),
+	REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a02c, 0x0000e808),
+	REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a030, 0x0003bd08),
+	REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a068, 0x000101d0),
+	REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a06c, 0x00055730),
+	REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a070, 0x0000000a),
+	REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a168, 0x00000006),
+
+	/* RP Control */
+	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa024, 0x00000b92),
+
+	/* HW RC6 Control */
+	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa090, 0x90040000),
+
+	/* Set RC6 VIDs */
+	REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GT_RETRY),
+	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138128, 0),
+	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138124, 0x80000004),
+	REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GT_RETRY),
+
+	/* Enable PM Interrupts */
+	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x4402c, 0x03000076),
+
+	/* Enable RC6 in idle */
+	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa094, 0x00040000),
+
+	REG_SCRIPT_END
+};
+
+static const struct reg_script broadwell_late_init_script[] = {
+	/* Lock settings */
+	REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a248, (1 << 31)),
+	REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a000, (1 << 18)),
+	REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a180, (1 << 31)),
+
+	/* Disable Force Wake */
+	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010000),
+	REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x130044, 1, 0, GT_RETRY),
+
+	/* Enable power well for DP and Audio */
+	REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x45400, (1 << 31)),
+	REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x45400,
+		       (1 << 30), (1 << 30), GT_RETRY),
+
+	REG_SCRIPT_END
+};
+
+u32 map_oprom_vendev(u32 vendev)
+{
+	return SA_IGD_OPROM_VENDEV;
+}
+
+static struct resource *gtt_res = NULL;
+
+static unsigned long gtt_read(unsigned long reg)
+{
+	u32 val;
+	val = read32(gtt_res->base + reg);
+	return val;
+
+}
+
+static void gtt_write(unsigned long reg, unsigned long data)
+{
+	write32(gtt_res->base + reg, data);
+}
+
+static inline void gtt_rmw(u32 reg, u32 andmask, u32 ormask)
+{
+	u32 val = gtt_read(reg);
+	val &= andmask;
+	val |= ormask;
+	gtt_write(reg, val);
+}
+
+static int gtt_poll(u32 reg, u32 mask, u32 value)
+{
+	unsigned try = GT_RETRY;
+	u32 data;
+
+	while (try--) {
+		data = gtt_read(reg);
+		if ((data & mask) == value)
+			return 1;
+		udelay(10);
+	}
+
+	printk(BIOS_ERR, "GT init timeout\n");
+	return 0;
+}
+
+static void igd_setup_panel(struct device *dev)
+{
+	config_t *conf = dev->chip_info;
+	u32 reg32;
+
+	/* Setup Digital Port Hotplug */
+	reg32 = gtt_read(PCH_PORT_HOTPLUG);
+	if (!reg32) {
+		reg32 = (conf->gpu_dp_b_hotplug & 0x7) << 2;
+		reg32 |= (conf->gpu_dp_c_hotplug & 0x7) << 10;
+		reg32 |= (conf->gpu_dp_d_hotplug & 0x7) << 18;
+		gtt_write(PCH_PORT_HOTPLUG, reg32);
+	}
+
+	/* Setup Panel Power On Delays */
+	reg32 = gtt_read(PCH_PP_ON_DELAYS);
+	if (!reg32) {
+		reg32 = (conf->gpu_panel_port_select & 0x3) << 30;
+		reg32 |= (conf->gpu_panel_power_up_delay & 0x1fff) << 16;
+		reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff);
+		gtt_write(PCH_PP_ON_DELAYS, reg32);
+	}
+
+	/* Setup Panel Power Off Delays */
+	reg32 = gtt_read(PCH_PP_OFF_DELAYS);
+	if (!reg32) {
+		reg32 = (conf->gpu_panel_power_down_delay & 0x1fff) << 16;
+		reg32 |= (conf->gpu_panel_power_backlight_off_delay & 0x1fff);
+		gtt_write(PCH_PP_OFF_DELAYS, reg32);
+	}
+
+	/* Setup Panel Power Cycle Delay */
+	if (conf->gpu_panel_power_cycle_delay) {
+		reg32 = gtt_read(PCH_PP_DIVISOR);
+		reg32 &= ~0xff;
+		reg32 |= conf->gpu_panel_power_cycle_delay & 0xff;
+		gtt_write(PCH_PP_DIVISOR, reg32);
+	}
+
+	/* Enable Backlight if needed */
+	if (conf->gpu_cpu_backlight) {
+		gtt_write(BLC_PWM_CPU_CTL2, BLC_PWM2_ENABLE);
+		gtt_write(BLC_PWM_CPU_CTL, conf->gpu_cpu_backlight);
+	}
+	if (conf->gpu_pch_backlight) {
+		gtt_write(BLC_PWM_PCH_CTL1, BLM_PCH_PWM_ENABLE);
+		gtt_write(BLC_PWM_PCH_CTL2, conf->gpu_pch_backlight);
+	}
+}
+
+static void igd_cdclk_init_haswell(struct device *dev)
+{
+	config_t *conf = dev->chip_info;
+	int cdclk = conf->cdclk;
+	int devid = pci_read_config16(dev, PCI_DEVICE_ID);
+	int gpu_is_ulx = 0;
+	u32 dpdiv, lpcll;
+
+	/* Check for ULX GT1 or GT2 */
+	if (devid == 0x0a0e || devid == 0x0a1e)
+		gpu_is_ulx = 1;
+
+	/* 675MHz is not supported on haswell */
+	if (cdclk == GT_CDCLK_675)
+		cdclk = GT_CDCLK_337;
+
+	/* If CD clock is fixed or ULT then set to 450MHz */
+	if ((gtt_read(0x42014) & 0x1000000) || cpu_is_ult())
+		cdclk = GT_CDCLK_450;
+
+	/* 540MHz is not supported on ULX */
+	if (gpu_is_ulx && cdclk == GT_CDCLK_540)
+		cdclk = GT_CDCLK_337;
+
+	/* 337.5MHz is not supported on non-ULT/ULX */
+	if (!gpu_is_ulx && !cpu_is_ult() && cdclk == GT_CDCLK_337)
+		cdclk = GT_CDCLK_450;
+
+	/* Set variables based on CD Clock setting */
+	switch (cdclk) {
+	case GT_CDCLK_337:
+		dpdiv = 169;
+		lpcll = (1 << 26);
+		break;
+	case GT_CDCLK_450:
+		dpdiv = 225;
+		lpcll = 0;
+		break;
+	case GT_CDCLK_540:
+		dpdiv = 270;
+		lpcll = (1 << 26);
+		break;
+	default:
+		return;
+	}
+
+	/* Set LPCLL_CTL CD Clock Frequency Select */
+	gtt_rmw(0x130040, 0xf3ffffff, lpcll);
+
+	/* ULX: Inform power controller of selected frequency */
+	if (gpu_is_ulx) {
+		if (cdclk == GT_CDCLK_450)
+			gtt_write(0x138128, 0x00000000); /* 450MHz */
+		else
+			gtt_write(0x138128, 0x00000001); /* 337.5MHz */
+		gtt_write(0x13812c, 0x00000000);
+		gtt_write(0x138124, 0x80000017);
+	}
+
+	/* Set CPU DP AUX 2X bit clock dividers */
+	gtt_rmw(0x64010, 0xfffff800, dpdiv);
+	gtt_rmw(0x64810, 0xfffff800, dpdiv);
+}
+
+static void igd_cdclk_init_broadwell(struct device *dev)
+{
+	config_t *conf = dev->chip_info;
+	int cdclk = conf->cdclk;
+	u32 dpdiv, lpcll, pwctl, cdset;
+
+	/* Inform power controller of upcoming frequency change */
+	gtt_write(0x138128, 0);
+	gtt_write(0x13812c, 0);
+	gtt_write(0x138124, 0x80000018);
+
+	/* Poll GT driver mailbox for run/busy clear */
+	if (!gtt_poll(0x138124, (1 << 31), (0 << 31)))
+		cdclk = GT_CDCLK_450;
+
+	if (gtt_read(0x42014) & 0x1000000) {
+		/* If CD clock is fixed then set to 450MHz */
+		cdclk = GT_CDCLK_450;
+	} else {
+		/* Program CD clock to highest supported freq */
+		if (cpu_is_ult())
+			cdclk = GT_CDCLK_540;
+		else
+			cdclk = GT_CDCLK_675;
+	}
+
+	/* CD clock frequency 675MHz not supported on ULT */
+	if (cpu_is_ult() && cdclk == GT_CDCLK_675)
+		cdclk = GT_CDCLK_540;
+
+	/* Set variables based on CD Clock setting */
+	switch (cdclk) {
+	case GT_CDCLK_337:
+		cdset = 337;
+		lpcll = (1 << 27);
+		pwctl = 2;
+		dpdiv = 169;
+		break;
+	case GT_CDCLK_450:
+		cdset = 449;
+		lpcll = 0;
+		pwctl = 0;
+		dpdiv = 225;
+		break;
+	case GT_CDCLK_540:
+		cdset = 539;
+		lpcll = (1 << 26);
+		pwctl = 1;
+		dpdiv = 270;
+		break;
+	case GT_CDCLK_675:
+		cdset = 674;
+		lpcll = (1 << 26) | (1 << 27);
+		pwctl = 3;
+		dpdiv = 338;
+	default:
+		return;
+	}
+
+	/* Set LPCLL_CTL CD Clock Frequency Select */
+	gtt_rmw(0x130040, 0xf3ffffff, lpcll);
+
+	/* Inform power controller of selected frequency */
+	gtt_write(0x138128, pwctl);
+	gtt_write(0x13812c, 0);
+	gtt_write(0x138124, 0x80000017);
+
+	/* Program CD Clock Frequency */
+	gtt_rmw(0x46200, 0xfffffc00, cdset);
+
+	/* Set CPU DP AUX 2X bit clock dividers */
+	gtt_rmw(0x64010, 0xfffff800, dpdiv);
+	gtt_rmw(0x64810, 0xfffff800, dpdiv);
+}
+
+static void igd_init(struct device *dev)
+{
+	int is_broadwell = !!(cpu_family_model() == BROADWELL_FAMILY_ULT);
+	u32 rp1_gfx_freq;
+
+	/* IGD needs to be Bus Master */
+	u32 reg32 = pci_read_config32(dev, PCI_COMMAND);
+	reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
+	pci_write_config32(dev, PCI_COMMAND, reg32);
+
+	gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0);
+	if (!gtt_res || !gtt_res->base)
+		return;
+
+	/* Wait for any configured pre-graphics delay */
+	mdelay(CONFIG_PRE_GRAPHICS_DELAY);
+
+	/* Early init steps */
+	if (is_broadwell) {
+		reg_script_run_on_dev(dev, broadwell_early_init_script);
+	} else {
+		reg_script_run_on_dev(dev, haswell_early_init_script);
+	}
+
+	/* Set RP1 graphics frequency */
+	rp1_gfx_freq = (MCHBAR32(0x5998) >> 8) & 0xff;
+	gtt_write(0xa008, rp1_gfx_freq << 24);
+
+	/* Post VBIOS panel setup */
+	igd_setup_panel(dev);
+
+	/* Initialize PCI device, load/execute BIOS Option ROM */
+	pci_dev_init(dev);
+
+	/* Late init steps */
+	if (is_broadwell) {
+		igd_cdclk_init_broadwell(dev);
+		reg_script_run_on_dev(dev, broadwell_late_init_script);
+	} else {
+		igd_cdclk_init_haswell(dev);
+		reg_script_run_on_dev(dev, haswell_late_init_script);
+	}
+}
+
+static void igd_read_resources(struct device *dev)
+{
+	pci_dev_read_resources(dev);
+
+#if CONFIG_MARK_GRAPHICS_MEM_WRCOMB
+	struct resource *res;
+
+	/* Set the graphics memory to write combining. */
+	res = find_resource(dev, PCI_BASE_ADDRESS_2);
+	if (res == NULL) {
+		printk(BIOS_DEBUG, "gma: memory resource not found.\n");
+		return;
+	}
+	res->flags |= IORESOURCE_WRCOMB;
+#endif
+}
+
+static struct device_operations igd_ops = {
+	.read_resources		= &igd_read_resources,
+	.set_resources		= &pci_dev_set_resources,
+	.enable_resources	= &pci_dev_enable_resources,
+	.init			= &igd_init,
+	.ops_pci		= &broadwell_pci_ops,
+};
+
+static const unsigned short pci_device_ids[] = {
+	IGD_HASWELL_ULT_GT1,
+	IGD_HASWELL_ULT_GT2,
+	IGD_HASWELL_ULT_GT3,
+	IGD_BROADWELL_U_GT1,
+	IGD_BROADWELL_U_GT2,
+	IGD_BROADWELL_U_GT3_15W,
+	IGD_BROADWELL_U_GT3_28W,
+	IGD_BROADWELL_Y_GT2,
+	IGD_BROADWELL_H_GT2,
+	IGD_BROADWELL_H_GT3,
+	0,
+};
+
+static const struct pci_driver igd_driver __pci_driver = {
+	.ops	 = &igd_ops,
+	.vendor	 = PCI_VENDOR_ID_INTEL,
+	.devices = pci_device_ids,
+};