diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2015-01-15 15:42:43 -0800 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-04-10 20:16:30 +0200 |
| commit | f059b241ad1ebd6b2084578b9284a19d018e8800 (patch) | |
| tree | 13175b038d5c2f15df63ee73360696cb9a7391d1 /src/soc/intel/broadwell/include | |
| parent | f9a6a82ea64074ba401213256011f4875b2763de (diff) | |
| download | coreboot-f059b241ad1ebd6b2084578b9284a19d018e8800.tar.xz | |
broadwell: Add function to apply PRR to a range of SPI flash
This function will use the next available/free protected range
register to cover the specified region of flash and write
protect it until the next reset.
This will be used by the common MRC cache code to protect the
RW_MRC_CACHE region after it is updated.
In order to communicate to the common NVM code that this function
is defined also enable CONFIG_MRC_SETTINGS_PROTECT variable.
BUG=chrome-os-partner:28234
BRANCH=broadwell
TEST=build and boot on samus
Change-Id: I710c6a69f725479411ed978cc615e1bb78fb42b8
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 25365433be0f190e10a96d9946b8ea90c883b78a
Original-Change-Id: I4a4cd27f9f4a94b9134dcba623f33b114299818f
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/241129
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/9493
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/broadwell/include')
| -rw-r--r-- | src/soc/intel/broadwell/include/soc/spi.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/soc/intel/broadwell/include/soc/spi.h b/src/soc/intel/broadwell/include/soc/spi.h index 8b95f70a5f..1449e29cda 100644 --- a/src/soc/intel/broadwell/include/soc/spi.h +++ b/src/soc/intel/broadwell/include/soc/spi.h @@ -35,6 +35,14 @@ #define SPIBAR_FDOC 0xb0 #define SPIBAR_FDOD 0xb4 +#define SPI_PRR_MAX 5 +#define SPI_PRR(x) (0x74 + ((x) * 4)) +#define SPI_PRR_SHIFT 12 +#define SPI_PRR_MASK 0x1fff +#define SPI_PRR_BASE_SHIFT 0 +#define SPI_PRR_LIMIT_SHIFT 16 +#define SPI_PRR_WPE (1 << 31) + #define SPIBAR_PREOP 0x94 #define SPIBAR_OPTYPE 0x96 #define SPIBAR_OPMENU_LOWER 0x98 @@ -97,4 +105,6 @@ #define SPIBAR_SSFC_DATA (1 << 14) #define SPIBAR_SSFC_GO (1 << 1) +int spi_flash_protect(u32 start, u32 size); + #endif |