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authorAaron Durbin <adurbin@chromium.org>2016-07-13 23:21:41 -0500
committerAaron Durbin <adurbin@chromium.org>2016-07-15 08:32:49 +0200
commit9e6d143a82a852ddfa64f20ceb8695939c1dace1 (patch)
tree147ee77b05213ace8941dbebe360df972f026517 /src/soc/intel/broadwell/include
parentc159bb0d76af801bca405e729c5f4b97a18a5a1d (diff)
downloadcoreboot-9e6d143a82a852ddfa64f20ceb8695939c1dace1.tar.xz
soc/intel/broadwell: use common Intel ACPI hardware definitions
Transition to using the common Intel ACPI hardware definitions generic ACPI definitions. BUG=chrome-os-partner:54977 Change-Id: I99d909ee72c3abebb1e9c8ebf44137465264bf0d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15673 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/broadwell/include')
-rw-r--r--src/soc/intel/broadwell/include/soc/pm.h14
1 files changed, 2 insertions, 12 deletions
diff --git a/src/soc/intel/broadwell/include/soc/pm.h b/src/soc/intel/broadwell/include/soc/pm.h
index 3f5bc40809..18004fa77d 100644
--- a/src/soc/intel/broadwell/include/soc/pm.h
+++ b/src/soc/intel/broadwell/include/soc/pm.h
@@ -16,6 +16,8 @@
#ifndef _BROADWELL_PM_H_
#define _BROADWELL_PM_H_
+#include <arch/acpi.h>
+
/* ACPI_BASE_ADDRESS / PMBASE */
#define PM1_STS 0x00
@@ -34,14 +36,6 @@
#define GBL_EN (1 << 5)
#define TMROF_EN (1 << 0)
#define PM1_CNT 0x04
-#define SLP_EN (1 << 13)
-#define SLP_TYP (7 << 10)
-#define SLP_TYP_SHIFT 10
-#define SLP_TYP_S0 0
-#define SLP_TYP_S1 1
-#define SLP_TYP_S3 5
-#define SLP_TYP_S4 6
-#define SLP_TYP_S5 7
#define GBL_RLS (1 << 2)
#define BM_RLD (1 << 1)
#define SCI_EN (1 << 0)
@@ -113,10 +107,6 @@
#define MAINBOARD_POWER_ON 1
#define MAINBOARD_POWER_KEEP 2
-#define SLEEP_STATE_S0 0
-#define SLEEP_STATE_S3 3
-#define SLEEP_STATE_S5 5
-
struct chipset_power_state {
uint16_t pm1_sts;
uint16_t pm1_en;