diff options
| author | Rizwan Qureshi <rizwan.qureshi@intel.com> | 2018-12-31 15:19:16 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-21 13:25:31 +0000 |
| commit | f9f50936446e8e441238ecfe12ce0fc9e04d491a (patch) | |
| tree | 2ce1ff776d013c72c8394da623f801facf7bd100 /src/soc/intel/broadwell/include | |
| parent | afe15f0a34fd02ef024d48d2b047ecd4ef559d74 (diff) | |
| download | coreboot-f9f50936446e8e441238ecfe12ce0fc9e04d491a.tar.xz | |
drivers/spi: Add controller protection type
Some SPI controllers support both READ and WRITE protection
add a variable to the protect API for the callers to specify
the kind of protection they want (Read/Write/Both).
Also, update the callers and protect API implementation.
BUG=None
BRANCH=None
TEST=test that the mrc cache is protected as expected on soraka.
Also tried if the read protection is applied correctly.
Change-Id: I093884c4768b08a378f21242ac82e430ac013d15
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/30559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/soc/intel/broadwell/include')
| -rw-r--r-- | src/soc/intel/broadwell/include/soc/spi.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/broadwell/include/soc/spi.h b/src/soc/intel/broadwell/include/soc/spi.h index 588af17609..5ad62fd19d 100644 --- a/src/soc/intel/broadwell/include/soc/spi.h +++ b/src/soc/intel/broadwell/include/soc/spi.h @@ -38,6 +38,7 @@ #define SPI_PRR_BASE_SHIFT 0 #define SPI_PRR_LIMIT_SHIFT 16 #define SPI_PRR_WPE (1 << 31) +#define SPI_PRR_RPE (1 << 15) #define SPIBAR_PREOP 0x94 #define SPIBAR_OPTYPE 0x96 |