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authorSumeet R Pawnikar <sumeet.r.pawnikar@intel.com>2020-05-08 22:18:09 +0530
committerPatrick Georgi <pgeorgi@google.com>2020-05-18 07:17:36 +0000
commitfa42d568a00e5daadd35722790c529539227130e (patch)
treec988cc49faf744bc499c837c1aadc569750709ae /src/soc/intel/broadwell/include
parent71a9a7c70f152e054294495a37f2c02b6b77cd84 (diff)
downloadcoreboot-fa42d568a00e5daadd35722790c529539227130e.tar.xz
broadwell: update processor power limits configuration
Update processor power limit configuration parameters based on common code base support for Intel Broadwell SoC based platforms. BRANCH=None BUG=None TEST=Build for broadwell based platform Change-Id: I97e38a533e74a122b6809e20a10f6e425827ab9c Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41234 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/broadwell/include')
-rw-r--r--src/soc/intel/broadwell/include/soc/cpu.h4
-rw-r--r--src/soc/intel/broadwell/include/soc/msr.h10
-rw-r--r--src/soc/intel/broadwell/include/soc/soc_chip.h20
3 files changed, 22 insertions, 12 deletions
diff --git a/src/soc/intel/broadwell/include/soc/cpu.h b/src/soc/intel/broadwell/include/soc/cpu.h
index 02605851ce..9167736c00 100644
--- a/src/soc/intel/broadwell/include/soc/cpu.h
+++ b/src/soc/intel/broadwell/include/soc/cpu.h
@@ -37,10 +37,6 @@
C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \
(IRTL_1024_NS >> 10))
-/* Configure power limits for turbo mode */
-void set_power_limits(u8 power_limit_1_time);
-int cpu_config_tdp_levels(void);
-
/* CPU identification */
u32 cpu_family_model(void);
u32 cpu_stepping(void);
diff --git a/src/soc/intel/broadwell/include/soc/msr.h b/src/soc/intel/broadwell/include/soc/msr.h
index 250f0f8336..1e47b4429e 100644
--- a/src/soc/intel/broadwell/include/soc/msr.h
+++ b/src/soc/intel/broadwell/include/soc/msr.h
@@ -3,6 +3,8 @@
#ifndef _BROADWELL_MSR_H_
#define _BROADWELL_MSR_H_
+#include <intelblocks/msr.h>
+
#define MSR_PIC_MSG_CONTROL 0x2e
#define MSR_CORE_THREAD_COUNT 0x35
#define MSR_PLATFORM_INFO 0xce
@@ -45,14 +47,6 @@
#define IRTL_RESPONSE_MASK (0x3ff)
#define MSR_COUNTER_24_MHZ 0x637
-/* long duration in low dword, short duration in high dword */
-#define MSR_PKG_POWER_LIMIT 0x610
-#define PKG_POWER_LIMIT_MASK 0x7fff
-#define PKG_POWER_LIMIT_EN (1 << 15)
-#define PKG_POWER_LIMIT_CLAMP (1 << 16)
-#define PKG_POWER_LIMIT_TIME_SHIFT 17
-#define PKG_POWER_LIMIT_TIME_MASK 0x7f
-
#define MSR_VR_CURRENT_CONFIG 0x601
#define MSR_VR_MISC_CONFIG 0x603
#define MSR_PKG_POWER_SKU_UNIT 0x606
diff --git a/src/soc/intel/broadwell/include/soc/soc_chip.h b/src/soc/intel/broadwell/include/soc/soc_chip.h
new file mode 100644
index 0000000000..ff77168e0a
--- /dev/null
+++ b/src/soc/intel/broadwell/include/soc/soc_chip.h
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_BROADWELL_SOC_CHIP_H_
+#define _SOC_BROADWELL_SOC_CHIP_H_
+
+#include "../../chip.h"
+
+#endif /* _SOC_BROADWELL_SOC_CHIP_H_ */