diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2017-03-16 19:00:37 -0700 |
|---|---|---|
| committer | Lee Leahy <leroy.p.leahy@intel.com> | 2017-03-17 18:03:59 +0100 |
| commit | 23602dfd6812dba0499318e1ec25492faa17febb (patch) | |
| tree | dec83ada3f60be39bbc7aa1fc3b1c0daf2b527bb /src/soc/intel/broadwell/include | |
| parent | 26b7cd0fa86562402b72509319a2b98ce8c21a8e (diff) | |
| download | coreboot-23602dfd6812dba0499318e1ec25492faa17febb.tar.xz | |
soc/intel/broadwell: Add int to unsigned
Fix the following issue detected by checkpatch:
WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
TEST=None
Change-Id: Iae22e724b6adae16248db7dc8f822f65bfadae5f
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18873
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Diffstat (limited to 'src/soc/intel/broadwell/include')
| -rw-r--r-- | src/soc/intel/broadwell/include/soc/gpio.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/include/soc/romstage.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/include/soc/smbus.h | 8 |
3 files changed, 6 insertions, 6 deletions
diff --git a/src/soc/intel/broadwell/include/soc/gpio.h b/src/soc/intel/broadwell/include/soc/gpio.h index ff51283709..7aba8dcf60 100644 --- a/src/soc/intel/broadwell/include/soc/gpio.h +++ b/src/soc/intel/broadwell/include/soc/gpio.h @@ -186,6 +186,6 @@ int gpio_is_native(int gpio_num); * Get a number comprised of multiple GPIO values. gpio_num_array points to * the array of gpio pin numbers to scan, terminated by -1. */ -unsigned get_gpios(const int *gpio_num_array); +unsigned int get_gpios(const int *gpio_num_array); #endif diff --git a/src/soc/intel/broadwell/include/soc/romstage.h b/src/soc/intel/broadwell/include/soc/romstage.h index e28d9b372f..ec733f855c 100644 --- a/src/soc/intel/broadwell/include/soc/romstage.h +++ b/src/soc/intel/broadwell/include/soc/romstage.h @@ -48,7 +48,7 @@ void pch_uart_init(void); void intel_early_me_status(void); void enable_smbus(void); -int smbus_read_byte(unsigned device, unsigned address); +int smbus_read_byte(unsigned int device, unsigned int address); int early_spi_read(u32 offset, u32 size, u8 *buffer); int early_spi_read_wpsr(u8 *sr); diff --git a/src/soc/intel/broadwell/include/soc/smbus.h b/src/soc/intel/broadwell/include/soc/smbus.h index 0a7dbaeeab..4d9d3e1f57 100644 --- a/src/soc/intel/broadwell/include/soc/smbus.h +++ b/src/soc/intel/broadwell/include/soc/smbus.h @@ -40,9 +40,9 @@ #define SMBUS_TIMEOUT (10 * 1000 * 100) #define SMBUS_SLAVE_ADDR 0x24 -int do_smbus_read_byte(unsigned smbus_base, unsigned device, - unsigned address); -int do_smbus_write_byte(unsigned smbus_base, unsigned device, - unsigned address, unsigned data); +int do_smbus_read_byte(unsigned int smbus_base, unsigned int device, + unsigned int address); +int do_smbus_write_byte(unsigned int smbus_base, unsigned int device, + unsigned int address, unsigned int data); #endif |