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| author | Kenji Chen <kenji.chen@intel.com> | 2014-09-26 03:14:57 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-02 17:27:48 +0200 |
| commit | e383feb7c8e1b46639c32df9a11fac6cf3d62403 (patch) | |
| tree | a9f78cc9d181b5c20ea608a8080673cdab07c181 /src/soc/intel/broadwell/iobp.c | |
| parent | c373f503dbbfc2a70e91f576fac01f66126556c2 (diff) | |
| download | coreboot-e383feb7c8e1b46639c32df9a11fac6cf3d62403.tar.xz | |
Broadwell: Synchronize for power management with FRC
Set Root Port 0 PCI CFG Offset 0xE2[5:4] before ASPM configuration.
BUG=chrome-os-partner:31424
TEST=Build an image, and check the procedure and recommended setting
is applied correctly.
Signed-off-by: Kenji Chen <kenji.chen@intel.com>
Change-Id: I94820787d4ed4a6bf8db8898b7de14467c9d6630
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 24bdea6cd67d5657b94058233cd26130f68c44e4
Original-Change-Id: I98713f615885ac02867942ece2be1cea8ce04ab2
Original-Reviewed-on: https://chromium-review.googlesource.com/219994
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Commit-Queue: Kenji Chen <kenji.chen@intel.com>
Original-Tested-by: Kenji Chen <kenji.chen@intel.com>
Reviewed-on: http://review.coreboot.org/9211
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/broadwell/iobp.c')
| -rw-r--r-- | src/soc/intel/broadwell/iobp.c | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/src/soc/intel/broadwell/iobp.c b/src/soc/intel/broadwell/iobp.c index 2bdd131707..a0b850eafd 100644 --- a/src/soc/intel/broadwell/iobp.c +++ b/src/soc/intel/broadwell/iobp.c @@ -123,3 +123,30 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) pch_iobp_write(address, data); } + +void pch_iobp_exec(u32 addr, u16 op_code, u8 route_id, u32 *data, u8 *resp) +{ + if (!data || !resp) + return; + + *resp = -1; + if (!iobp_poll()) + return; + + /* RCBA2330[31:0] = Address */ + RCBA32(IOBPIRI) = addr; + /* RCBA2338[15:8] = opcode */ + RCBA16(IOBPS) = (RCBA16(IOBPS) & 0x00ff) | op_code; + /* RCBA233A[15:8] = 0xf0 RCBA233A[7:0] = Route ID */ + RCBA16(IOBPU) = IOBPU_MAGIC | route_id; + + RCBA32(IOBPD) = *data; + /* Set RCBA2338[0] to trigger IOBP transaction*/ + RCBA16(IOBPS) = RCBA16(IOBPS) | 0x1; + + if (!iobp_poll()) + return; + + *resp = (RCBA16(IOBPS) & IOBPS_TX_MASK) >> 1; + *data = RCBA32(IOBPD); +} |