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| author | Duncan Laurie <dlaurie@chromium.org> | 2017-11-11 20:03:29 -0800 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2017-11-15 16:07:21 +0000 |
| commit | 93bbd41ea8ece8bb4e502a62e14f96653017e911 (patch) | |
| tree | 1b7394af2c4cb868dce51cd4aa88774243069dc8 /src/soc/intel/broadwell/lpc.c | |
| parent | e4a36c7b52d6528c3a8035f6ccdf6b4da1f56f58 (diff) | |
| download | coreboot-93bbd41ea8ece8bb4e502a62e14f96653017e911.tar.xz | |
soc/intel: Enable ACPI DBG2 table generation
Enable the ACPI DBG2 table generation for Intel boards. This is
a Microsoft defined ACPI extension that allows an OS to know what
the debug port is on a system when it is not enabled by the
firmware, so it does not show up in the coreboot tables and
cannot be easily found by a payload.
broadwell: Use byte access device, set up only when enabled since
it relies on the port being put in byte access mode and using
this serial port for debug was not standard in this generation.
skylake: Enable for the configured debug port. Skylake uses
intelblocks for UART but not ACPI.
common: Enable for the configured debug port. This affects
apollolake and cannonlake.
Tested by compiling for apollolake/broadwell, tested by reading
the DBG2 ACPI table on kabylake board and using IASL to dump:
[000h 0000 4] Signature : "DBG2"
[004h 0004 4] Table Length : 00000061
[008h 0008 1] Revision : 00
[009h 0009 1] Checksum : 3B
[00Ah 0010 6] Oem ID : "CORE "
[010h 0016 8] Oem Table ID : "COREBOOT"
[018h 0024 4] Oem Revision : 00000000
[01Ch 0028 4] Asl Compiler ID : "CORE"
[020h 0032 4] Asl Compiler Revision : 00000000
[024h 0036 4] Info Offset : 0000002C
[028h 0040 4] Info Count : 00000001
[02Ch 0044 1] Revision : 00
[02Dh 0045 2] Length : 0035
[02Fh 0047 1] Register Count : 01
[030h 0048 2] Namepath Length : 000F
[032h 0050 2] Namepath Offset : 0026
[034h 0052 2] OEM Data Length : 0000
[036h 0054 2] OEM Data Offset : 0000
[038h 0056 2] Port Type : 8000
[03Ah 0058 2] Port Subtype : 0000
[03Ch 0060 2] Reserved : 0000
[03Eh 0062 2] Base Address Offset : 0016
[040h 0064 2] Address Size Offset : 0022
[042h 0066 12] Base Address Register : [Generic Address Structure]
[042h 0066 1] Space ID : 00 [SystemMemory]
[043h 0067 1] Bit Width : 00
[044h 0068 1] Bit Offset : 00
[045h 0069 1] Encoded Access Width : 03 [DWord Access:32]
[046h 0070 8] Address : 00000000FE034000
[04Eh 0078 4] Address Size : 00001000
[052h 0082 15] Namepath : "\_SB.PCI0.UAR2"
Change-Id: If34a3d2252896e0b0f762136760ab981afc12a2f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/22453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/broadwell/lpc.c')
| -rw-r--r-- | src/soc/intel/broadwell/lpc.c | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index d502e956e3..d1c42423ae 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -601,12 +601,24 @@ static void southcluster_inject_dsdt(device_t device) } } +static unsigned long broadwell_write_acpi_tables(device_t device, + unsigned long current, + struct acpi_rsdp *rsdp) +{ + if (IS_ENABLED(CONFIG_INTEL_PCH_UART_CONSOLE)) + current = acpi_write_dbg2_pci_uart(rsdp, current, + (CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER == 1) ? + PCH_DEV_UART1 : PCH_DEV_UART0, + ACPI_ACCESS_SIZE_BYTE_ACCESS); + return acpi_write_hpet(device, current, rsdp); +} + static struct device_operations device_ops = { .read_resources = &pch_lpc_read_resources, .set_resources = &pci_dev_set_resources, .enable_resources = &pci_dev_enable_resources, .acpi_inject_dsdt_generator = southcluster_inject_dsdt, - .write_acpi_tables = acpi_write_hpet, + .write_acpi_tables = broadwell_write_acpi_tables, .init = &lpc_init, .scan_bus = &scan_lpc_bus, .ops_pci = &broadwell_pci_ops, |