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| author | Aaron Durbin <adurbin@chromium.org> | 2017-09-15 11:51:58 -0600 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-09-20 23:53:44 +0000 |
| commit | b9d9b79cedebcbcd46bd457ab2f70239a22ab572 (patch) | |
| tree | 45834f05b24e276943e63f62ced6c4aaf60edfa7 /src/soc/intel/broadwell/lpc.c | |
| parent | 3118b6277d743100a4a0718edbfea02ddb50f625 (diff) | |
| download | coreboot-b9d9b79cedebcbcd46bd457ab2f70239a22ab572.tar.xz | |
soc/intel/broadwell: refactor rtc failure checking
In order to prepare for checking RTC failure in the early boot
paths move the rtc failure calculation to pmutil.c and add a helper
function to determine if failure occurred.
BUG=b:63054105
Change-Id: Ia0a38f00d2a5c7270e24bdd35ecab7fbba1016d4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/broadwell/lpc.c')
| -rw-r--r-- | src/soc/intel/broadwell/lpc.c | 13 |
1 files changed, 1 insertions, 12 deletions
diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index ac80cbeb0d..d502e956e3 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -180,18 +180,7 @@ static void pch_power_options(device_t dev) static void pch_rtc_init(struct device *dev) { - u8 reg8; - int rtc_failed; - - reg8 = pci_read_config8(dev, GEN_PMCON_3); - rtc_failed = reg8 & RTC_BATTERY_DEAD; - if (rtc_failed) { - reg8 &= ~RTC_BATTERY_DEAD; - pci_write_config8(dev, GEN_PMCON_3, reg8); - printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed); - } - - cmos_init(rtc_failed); + cmos_init(rtc_failure()); } static const struct reg_script pch_misc_init_script[] = { |