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authorPatrick Georgi <pgeorgi@chromium.org>2015-04-22 13:32:13 +0200
committerPatrick Georgi <pgeorgi@google.com>2015-04-22 19:36:08 +0200
commit320ad820aa01c6ac4b7b42d155c59709b2e192bc (patch)
tree70fbf251561b21bed5d4979aa5982c49376a2061 /src/soc/intel/broadwell/lpc.c
parentbd74a4b2d25268f7035a4478da31f27baac2aecc (diff)
downloadcoreboot-320ad820aa01c6ac4b7b42d155c59709b2e192bc.tar.xz
intel/broadwell: guard CHROMEOS support better
Since CHROMEOS_VBNV_* are selected by mainboards, they may be active without CHROMEOS being selected. In this case, they should be a no-op. Change-Id: I3b84e2a919ffaa809d713e72e5e4df7a7575e6b9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9954 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/intel/broadwell/lpc.c')
-rw-r--r--src/soc/intel/broadwell/lpc.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c
index 9a4c65c8f3..6cc11165c3 100644
--- a/src/soc/intel/broadwell/lpc.c
+++ b/src/soc/intel/broadwell/lpc.c
@@ -178,7 +178,7 @@ static void pch_power_options(device_t dev)
enable_alt_smi(config->alt_gp_smi_en);
}
-#if IS_ENABLED(CONFIG_CHROMEOS_VBNV_CMOS)
+#if IS_ENABLED(CONFIG_CHROMEOS) && IS_ENABLED(CONFIG_CHROMEOS_VBNV_CMOS)
/*
* Preserve Vboot NV data when clearing CMOS as it will
* have been re-initialized already by Vboot firmware init.
@@ -210,7 +210,7 @@ static void pch_rtc_init(struct device *dev)
printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
}
-#if IS_ENABLED(CONFIG_CHROMEOS_VBNV_CMOS)
+#if IS_ENABLED(CONFIG_CHROMEOS) && IS_ENABLED(CONFIG_CHROMEOS_VBNV_CMOS)
pch_cmos_init_preserve(rtc_failed);
#else
cmos_init(rtc_failed);