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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-04-29 10:42:34 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-01 16:35:06 +0000 |
| commit | b887adf7a56f2877c41e808002f30841a6679eb6 (patch) | |
| tree | 21610d86c82b79f9c72e89b4be09fac4035d2505 /src/soc/intel/broadwell/me.c | |
| parent | 3e42ee05d86c1de3ed23dddf08fd8e6451bdea92 (diff) | |
| download | coreboot-b887adf7a56f2877c41e808002f30841a6679eb6.tar.xz | |
soc/intel/broadwell: Fix 16-bit read/write PCI_COMMAND register
Change-Id: I0fd1a758d8838b3eea5640b41eee6a6893360aa3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/broadwell/me.c')
| -rw-r--r-- | src/soc/intel/broadwell/me.c | 13 |
1 files changed, 5 insertions, 8 deletions
diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c index 730d77ed14..afe9c82705 100644 --- a/src/soc/intel/broadwell/me.c +++ b/src/soc/intel/broadwell/me.c @@ -600,17 +600,17 @@ static int mkhi_hmrfpo_lock_noack(void) static void intel_me_finalize(struct device *dev) { - u32 reg32; + u16 reg16; /* S3 path will have hidden this device already */ if (!mei_base_address || mei_base_address == (u8 *) 0xfffffff0) return; /* Make sure IO is disabled */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_write_config16(dev, PCI_COMMAND, reg16); /* Hide the PCI device */ RCBA32_OR(FD2, PCH_DISABLE_MEI1); @@ -712,7 +712,6 @@ static int intel_mei_setup(struct device *dev) { struct resource *res; struct mei_csr host; - u32 reg32; /* Find the MMIO base for the ME interface */ res = find_resource(dev, PCI_BASE_ADDRESS_0); @@ -723,9 +722,7 @@ static int intel_mei_setup(struct device *dev) mei_base_address = res2mmio(res, 0, 0); /* Ensure Memory and Bus Master bits are set */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); /* Clean up status for next message */ read_host_csr(&host); |