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| author | Duncan Laurie <dlaurie@chromium.org> | 2014-08-26 13:49:24 -0700 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2015-03-27 06:25:16 +0100 |
| commit | a7d8ea84c63e9c8103a6a8bc45b3aa92658a028f (patch) | |
| tree | aa35fb666809baf1ba6e8efeac504f57a766d8fd /src/soc/intel/broadwell/me_status.c | |
| parent | edb55fc0ad232b666684977ba4f0fece4a858ffb (diff) | |
| download | coreboot-a7d8ea84c63e9c8103a6a8bc45b3aa92658a028f.tar.xz | |
broadwell: Read and save HSIO version from ME in romstage
This can be used to know if HSIO registers need updating in ramstage
but it is not possible to query the ME for HSIO version after sending
the DRAM-init-done message.
BUG=chrome-os-partner:28234
BRANCH=samus
TEST=build and boot on samus, check for HSIO version messages in log
Original-Change-Id: Id6beeaf57287e8826b9f142f768636a9c055d7eb
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214259
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 637cbf5c1a1d922dab3f8a5cd4b3cd05617d1b92)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I29ce907804e892afde5f91e0b21688a50217cf13
Reviewed-on: http://review.coreboot.org/8966
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/soc/intel/broadwell/me_status.c')
| -rw-r--r-- | src/soc/intel/broadwell/me_status.c | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/src/soc/intel/broadwell/me_status.c b/src/soc/intel/broadwell/me_status.c index 3738fd4c8b..4dfbeaec75 100644 --- a/src/soc/intel/broadwell/me_status.c +++ b/src/soc/intel/broadwell/me_status.c @@ -25,6 +25,7 @@ #include <string.h> #include <broadwell/pci_devs.h> #include <broadwell/me.h> +#include <delay.h> #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) @@ -279,3 +280,38 @@ void intel_me_status(void) printk(BIOS_DEBUG, "\n"); } #endif + +void intel_me_hsio_version(uint16_t *version, uint16_t *checksum) +{ + int count; + u32 hsiover; + struct me_hfs hfs; + + /* Query for HSIO version, overloads H_GS and HFS */ + pci_write_config32(PCH_DEV_ME, PCI_ME_H_GS, + ME_HSIO_MESSAGE | ME_HSIO_CMD_GETHSIOVER); + + /* Must wait for ME acknowledgement */ + for (count = ME_RETRY; count > 0; --count) { + me_read_dword_ptr(&hfs, PCI_ME_HFS); + if (hfs.bios_msg_ack) + break; + udelay(ME_DELAY); + } + if (!count) { + printk(BIOS_ERR, "ERROR: ME failed to respond\n"); + return; + } + + /* HSIO version should be in HFS_5 */ + hsiover = pci_read_config32(PCH_DEV_ME, PCI_ME_HFS5); + *version = hsiover >> 16; + *checksum = hsiover & 0xffff; + + printk(BIOS_DEBUG, "ME: HSIO Version : %d (CRC 0x%04x)\n", + *version, *checksum); + + /* Reset registers to normal behavior */ + pci_write_config32(PCH_DEV_ME, PCI_ME_H_GS, + ME_HSIO_MESSAGE | ME_HSIO_CMD_GETHSIOVER); +} |