diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-04-29 10:42:34 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-01 16:35:06 +0000 |
| commit | b887adf7a56f2877c41e808002f30841a6679eb6 (patch) | |
| tree | 21610d86c82b79f9c72e89b4be09fac4035d2505 /src/soc/intel/broadwell/pch.c | |
| parent | 3e42ee05d86c1de3ed23dddf08fd8e6451bdea92 (diff) | |
| download | coreboot-b887adf7a56f2877c41e808002f30841a6679eb6.tar.xz | |
soc/intel/broadwell: Fix 16-bit read/write PCI_COMMAND register
Change-Id: I0fd1a758d8838b3eea5640b41eee6a6893360aa3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/broadwell/pch.c')
| -rw-r--r-- | src/soc/intel/broadwell/pch.c | 12 |
1 files changed, 5 insertions, 7 deletions
diff --git a/src/soc/intel/broadwell/pch.c b/src/soc/intel/broadwell/pch.c index f6f3746d0e..ac6ac2ad7f 100644 --- a/src/soc/intel/broadwell/pch.c +++ b/src/soc/intel/broadwell/pch.c @@ -171,7 +171,7 @@ void pch_disable_devfn(struct device *dev) void broadwell_pch_enable_dev(struct device *dev) { - u32 reg32; + u16 reg16; /* These devices need special enable/disable handling */ switch (PCI_SLOT(dev->path.pci.devfn)) { @@ -185,18 +185,16 @@ void broadwell_pch_enable_dev(struct device *dev) printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); /* Ensure memory, io, and bus master are all disabled */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_write_config16(dev, PCI_COMMAND, reg16); /* Disable this device if possible */ pch_disable_devfn(dev); } else { /* Enable SERR */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); } } |