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| author | Angel Pons <th3fanbus@gmail.com> | 2020-10-25 14:01:06 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-11-04 22:59:42 +0000 |
| commit | 040f3be59e592311bf7d8f658b2cca1189d62f2c (patch) | |
| tree | b9a1b8fa950a0a179691c15369130028483f900a /src/soc/intel/broadwell/pch/acpi/lpc.asl | |
| parent | a42d37ac3f8bf5ffdfa7f2d3416d35769b65dc3b (diff) | |
| download | coreboot-040f3be59e592311bf7d8f658b2cca1189d62f2c.tar.xz | |
soc/intel/broadwell: Include EC and IRQ links ACPI early
Other southbridges such as Lynx Point do it. This eases merging later.
Change-Id: I10196bbc44ce859c2747755845378351f45944ae
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46766
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/broadwell/pch/acpi/lpc.asl')
| -rw-r--r-- | src/soc/intel/broadwell/pch/acpi/lpc.asl | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/soc/intel/broadwell/pch/acpi/lpc.asl b/src/soc/intel/broadwell/pch/acpi/lpc.asl index 01e1bebaf9..0af85e62cc 100644 --- a/src/soc/intel/broadwell/pch/acpi/lpc.asl +++ b/src/soc/intel/broadwell/pch/acpi/lpc.asl @@ -31,6 +31,10 @@ Device (LPCB) IOD1, 8, } + #include <southbridge/intel/common/acpi/irqlinks.asl> + + #include "acpi/ec.asl" + Device (DMAC) // DMA Controller { Name (_HID, EISAID("PNP0200")) @@ -180,7 +184,5 @@ Device (LPCB) } #include "gpio.asl" - #include <southbridge/intel/common/acpi/irqlinks.asl> - #include "acpi/ec.asl" #include "acpi/superio.asl" } |