diff options
author | Angel Pons <th3fanbus@gmail.com> | 2020-10-25 21:11:58 +0100 |
---|---|---|
committer | Michael Niewöhner <foss@mniewoehner.de> | 2020-11-13 12:02:43 +0000 |
commit | 56d37fbe6f65d6c92a082d30baf13e79331dcebd (patch) | |
tree | 86f387f2f117828125e840f808188ece09480d61 /src/soc/intel/broadwell/pch/acpi/pch.asl | |
parent | e53dfe0cfba9a773079a7229b05ed4b4c5e9e3c4 (diff) | |
download | coreboot-56d37fbe6f65d6c92a082d30baf13e79331dcebd.tar.xz |
soc/intel/broadwell/pch/acpi: Clean up cosmetics
Use ASL 2.0 syntax where possible and uniformize code style to match the
IASL disassembly. Some `Store` in gpio.asl change the binary if touched.
Tested with BUILD_TIMELESS=1, Google Buddy does not change.
Change-Id: Ic13c081fd7ee2212d851cc14263c1e2fd8970072
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46778
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/broadwell/pch/acpi/pch.asl')
-rw-r--r-- | src/soc/intel/broadwell/pch/acpi/pch.asl | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/intel/broadwell/pch/acpi/pch.asl b/src/soc/intel/broadwell/pch/acpi/pch.asl index 7b57859672..d68fa60bbf 100644 --- a/src/soc/intel/broadwell/pch/acpi/pch.asl +++ b/src/soc/intel/broadwell/pch/acpi/pch.asl @@ -29,8 +29,8 @@ Scope (\) */ Method (ISWP) { - And (\_SB.PCI0.LPCB.PDID, 0xfff0, Local0) - If (LEqual (Local0, 0x9cc0)) { + Local0 = \_SB.PCI0.LPCB.PDID & 0xfff0 + If (Local0 == 0x9cc0) { Return (1) } Else { Return (0) @@ -68,7 +68,7 @@ Scope (\) Method (_OSC, 4) { /* Check for proper GUID */ - If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + If (Arg0 == ToUUID ("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { /* Let OS control everything */ Return (Arg3) @@ -77,7 +77,7 @@ Method (_OSC, 4) { /* Unrecognized UUID */ CreateDWordField (Arg3, 0, CDW1) - Or (CDW1, 4, CDW1) + CDW1 |= 4 Return (Arg3) } } |