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| author | Martin Roth <martin.roth@se-eng.com> | 2014-12-07 14:58:18 -0700 |
|---|---|---|
| committer | Martin Roth <gaumless@gmail.com> | 2014-12-08 05:38:54 +0100 |
| commit | de7ed6fc7cdb3f55894e613bdc0c394fa8f57494 (patch) | |
| tree | 773464cb40de3a87a9921db6c15668cd3c889b11 /src/soc/intel/broadwell/pcie.c | |
| parent | 8ff0ead0816dfc2683ee93e2f5eef79e007a5cd6 (diff) | |
| download | coreboot-de7ed6fc7cdb3f55894e613bdc0c394fa8f57494.tar.xz | |
intel/broadwell: Spelling fixes
Change-Id: I2f970c6970b4996fcefbde89332210f5a1afe836
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7702
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/soc/intel/broadwell/pcie.c')
| -rw-r--r-- | src/soc/intel/broadwell/pcie.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index a407f3c686..f167ca3bf4 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -417,21 +417,21 @@ static void pch_pcie_early(struct device *dev) case 3: case 4: /* - * Bits 31:28 of b0d28f0 0x32c register correspnd to + * Bits 31:28 of b0d28f0 0x32c register correspond to * Root Ports 4:1. */ do_aspm = !!(rpc.b0d28f0_32c & (1 << (28 + rp - 1))); break; case 5: /* - * Bit 28 of b0d28f4 0x32c register correspnd to + * Bit 28 of b0d28f4 0x32c register correspond to * Root Ports 4:1. */ do_aspm = !!(rpc.b0d28f4_32c & (1 << 28)); break; case 6: /* - * Bit 28 of b0d28f5 0x32c register correspnd to + * Bit 28 of b0d28f5 0x32c register correspond to * Root Ports 4:1. */ do_aspm = !!(rpc.b0d28f5_32c & (1 << 28)); @@ -509,7 +509,7 @@ static void pch_pcie_early(struct device *dev) pcie_update_cfg(dev, 0x33c, ~0x00ffffff, 0x854c74); - /* Set Invalid Recieve Range Check Enable in MPC register. */ + /* Set Invalid Receive Range Check Enable in MPC register. */ pcie_update_cfg(dev, 0xd8, ~0, (1 << 25)); pcie_update_cfg8(dev, 0xf5, 0x3f, 0); |