diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2014-08-08 09:59:43 -0700 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2015-03-27 05:39:35 +0100 |
| commit | 446fb8e45ef2d555579e7659c1c0a91bb8ff3d78 (patch) | |
| tree | c610b4353948d3826b1402a5bc6b1da3da35cff6 /src/soc/intel/broadwell/pcie.c | |
| parent | 3deaa058502d9cea14fd198c3280d85f1bd2f3a2 (diff) | |
| download | coreboot-446fb8e45ef2d555579e7659c1c0a91bb8ff3d78.tar.xz | |
broadwell: Misc updates from 2.1.0 ref code
- ADSP IRQ should be exclusive
- HDA should write reg 0x43 even if disabled
- A few clock gating tweaks based on ref code changes
- Move SATA clock gating to sata.c where SIR changes are done
- Add support for enabling Deep SX in AC/DC modes
- CLKREQ VR Idle for enabled PCIE ports
BUG=chrome-os-partner:28234
BRANCH=None
TEST=build and boot on samus
Original-Change-Id: Icece58e32b7a5d2b359debd5516a230cae3fd48c
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/211611
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit c0e22ba043ed96bdddca4989b2f29d0e989f6fef)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: If5f5e1666aa9660e31305ee6369f2febf6757b99
Reviewed-on: http://review.coreboot.org/8952
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/soc/intel/broadwell/pcie.c')
| -rw-r--r-- | src/soc/intel/broadwell/pcie.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index f167ca3bf4..a251a17a89 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -226,6 +226,9 @@ static void pcie_enable_clock_gating(void) /* Configure shared resource clock gating. */ if (rp == 1 || rp == 5 || rp == 6) pcie_update_cfg8(dev, 0xe1, 0xc3, 0x3c); + + /* CLKREQ# VR Idle Enable */ + RCBA32_OR(0x2b1c, (1 << (16 + i))); } if (!enabled_ports) |