diff options
| author | Julius Werner <jwerner@chromium.org> | 2019-03-05 16:53:33 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-08 08:33:24 +0000 |
| commit | cd49cce7b70e80b4acc49b56bb2bb94370b4d867 (patch) | |
| tree | 8e89136e2da7cf54453ba8c112eda94415b56242 /src/soc/intel/broadwell/pcie.c | |
| parent | b3a8cc54dbaf833c590a56f912209a5632b71f49 (diff) | |
| download | coreboot-cd49cce7b70e80b4acc49b56bb2bb94370b4d867.tar.xz | |
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/broadwell/pcie.c')
| -rw-r--r-- | src/soc/intel/broadwell/pcie.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index 3fd5ea4f10..32135eedbb 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -555,7 +555,7 @@ static void pch_pcie_early(struct device *dev) pci_update_config8(dev, 0xf5, 0x0f, 0); /* Set AER Extended Cap ID to 01h and Next Cap Pointer to 200h. */ - if (IS_ENABLED(CONFIG_PCIEXP_AER)) + if (CONFIG(PCIEXP_AER)) pci_update_config32(dev, 0x100, ~(1 << 29) & ~0xfffff, (1 << 29) | 0x10001); else @@ -563,7 +563,7 @@ static void pch_pcie_early(struct device *dev) (1 << 29)); /* Set L1 Sub-State Cap ID to 1Eh and Next Cap Pointer to None. */ - if (IS_ENABLED(CONFIG_PCIEXP_L1_SUB_STATE)) + if (CONFIG(PCIEXP_L1_SUB_STATE)) pci_update_config32(dev, 0x200, ~0xfffff, 0x001e); else pci_update_config32(dev, 0x200, ~0xfffff, 0); |