broadwell: ACPI, romstage, and other updates

broadwell: Add romstage usbdebug support
Reviewed-on: https://chromium-review.googlesource.com/199412
(cherry picked from commit 1050e7d3be6ec1e4fe5aa2df408f4bb6d33a42b5)

broadwell: Add romstage code to configure PCH UART for console
Reviewed-on: https://chromium-review.googlesource.com/199807
(cherry picked from commit ecebda4eb5d6fe58473d25c2898ba1a2eac0f39a)

broadwell: Expand the PCI device convenience macros
Reviewed-on: https://chromium-review.googlesource.com/199891
(cherry picked from commit f8c54c70f136cd2cb8f977bc25661974d7e529ad)

broadwell: Add ramstage driver for ADSP
Reviewed-on: https://chromium-review.googlesource.com/199892
(cherry picked from commit e8e986b0ba52bbfc9923d71009fbd31e749ca43f)

broadwell: Update ACPI devices
Reviewed-on: https://chromium-review.googlesource.com/201080
(cherry picked from commit 2446b35578eb36e0009415bec340059135751549)

broadwell: Reserve DPR region
Reviewed-on: https://chromium-review.googlesource.com/201081
(cherry picked from commit 8ecd9d2096db2bded6f27ef6ee9a9b39ce2dfec6)

broadwell: Remove old pei_data and add cpu function for romstage
Reviewed-on: https://chromium-review.googlesource.com/201690
(cherry picked from commit d206c9cdd69519d502a90bb0595f0e3a7cb50274)

broadwell: Fixes for graphics without executing VBIOS
Reviewed-on: https://chromium-review.googlesource.com/202356
(cherry picked from commit 0c031df1ce92c875e95ddfd3f026f649c342c7fa)

broadwell: Fix compilation failure when loglevel is lowered
Reviewed-on: https://chromium-review.googlesource.com/202357
(cherry picked from commit 708ce78b2bfae5664b1238e17b086c88cac55bdc)

broadwell: Disable GPIO controller interrupt
Reviewed-on: https://chromium-review.googlesource.com/203645
(cherry picked from commit 2d17e98eded5958258ba5c0abf600284d8d03af9)

broadwell: Add support for E0 stepping
Reviewed-on: https://chromium-review.googlesource.com/205160
(cherry picked from commit 802e9d371418cc7a7fc7af131d7e5dda0ae5b273)

broadwell: misc updates for CPU driver
Reviewed-on: https://chromium-review.googlesource.com/205161
(cherry picked from commit ea1d403817ee193648f2c119fd45894e32e57e97)

broadwell: Read power state earlier and store in romstage params
Reviewed-on: https://chromium-review.googlesource.com/208151
(cherry picked from commit b2198d71084ad3c1360a0bfedc46c8dd3825bd0e)

broadwell: Add parameters to pei_data structure
Reviewed-on: https://chromium-review.googlesource.com/208153
(cherry picked from commit 423fbf67e497a907fbc8e12caf2929d4951858af)

broadwell: Move platform report output after power state is read
Reviewed-on: https://chromium-review.googlesource.com/208213
(cherry picked from commit acedf4146bf9377133433046dae1fa9c8bc69d78)

Squashed 15 commits for broadwell support.

Change-Id: I87e320d3d5376b84dd9c146b0b833e5ce53244aa
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6982
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>

1 files changed, 0 insertions, 115 deletions

diff --git a/src/soc/intel/broadwell/pei_data.h b/src/soc/intel/broadwell/pei_data.h
deleted file mode 100644
index f92c0a68e0..0000000000
--- a/src/soc/intel/broadwell/pei_data.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * coreboot UEFI PEI wrapper
- *
- * Copyright (c) 2011, Google Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Google Inc. nor the
- *       names of its contributors may be used to endorse or promote products
- *       derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL GOOGLE INC BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef PEI_DATA_H
-#define PEI_DATA_H
-
-typedef void (*tx_byte_func)(unsigned char byte);
-#define PEI_VERSION 15
-
-#define MAX_USB2_PORTS 16
-#define MAX_USB3_PORTS 16
-#define USB_OC_PIN_SKIP 8
-
-enum usb2_port_location {
-	USB_PORT_BACK_PANEL = 0,
-	USB_PORT_FRONT_PANEL,
-	USB_PORT_DOCK,
-	USB_PORT_MINI_PCIE,
-	USB_PORT_FLEX,
-	USB_PORT_INTERNAL,
-	USB_PORT_SKIP
-};
-
-/* Usb Port Length:
- * [16:4] = length in inches in octal format
- * [3:0]  = decimal point
- */
-struct usb2_port_setting {
-	uint16_t length;
-	uint8_t enable;
-	uint8_t over_current_pin;
-	uint8_t location;
-} __attribute__((packed));
-
-struct usb3_port_setting {
-	uint8_t enable;
-	uint8_t over_current_pin;
-} __attribute__((packed));
-
-struct pei_data
-{
-	uint32_t pei_version;
-	uint32_t mchbar;
-	uint32_t dmibar;
-	uint32_t epbar;
-	uint32_t pciexbar;
-	uint16_t smbusbar;
-	uint32_t wdbbar;
-	uint32_t wdbsize;
-	uint32_t hpet_address;
-	uint32_t rcba;
-	uint32_t pmbase;
-	uint32_t gpiobase;
-	uint32_t temp_mmio_base;
-	uint32_t system_type; // 0 Mobile, 1 Desktop/Server
-	uint32_t tseg_size;
-	uint8_t spd_addresses[4];
-	int boot_mode;
-	int ec_present;
-	int gbe_enable;
-	// 0 = leave channel enabled
-	// 1 = disable dimm 0 on channel
-	// 2 = disable dimm 1 on channel
-	// 3 = disable dimm 0+1 on channel
-	int dimm_channel0_disabled;
-	int dimm_channel1_disabled;
-	/* Enable 2x Refresh Mode */
-	int ddr_refresh_2x;
-	int dq_pins_interleaved;
-	/* Data read from flash and passed into MRC */
-	unsigned char *mrc_input;
-	unsigned int mrc_input_len;
-	/* Data from MRC that should be saved to flash */
-	unsigned char *mrc_output;
-	unsigned int mrc_output_len;
-	/*
-	 * Max frequency DDR3 could be ran at. Could be one of four values: 800,
-	 * 1067, 1333, 1600
-	 */
-	uint32_t max_ddr3_freq;
-	/* Route all USB ports to XHCI controller in resume path */
-	int usb_xhci_on_resume;
-	struct usb2_port_setting usb2_ports[MAX_USB2_PORTS];
-	struct usb3_port_setting usb3_ports[MAX_USB3_PORTS];
-	uint8_t spd_data[4][256];
-	tx_byte_func tx_byte;
-} __attribute__((packed));
-
-#endif