diff options
author | Duncan Laurie <dlaurie@chromium.org> | 2014-09-29 08:51:45 -0700 |
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committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-04-10 19:22:25 +0200 |
commit | 1fad694953add0af54721647e5be360045987142 (patch) | |
tree | 344ac17574523a2b6accc66c63044dd6c9f7a6ef /src/soc/intel/broadwell/ramstage.c | |
parent | 9afc5c05f083631424e4e6a86a6c08fcc3e6473b (diff) | |
download | coreboot-1fad694953add0af54721647e5be360045987142.tar.xz |
broadwell: Add support for ACPI \_GPE._SWS
In order to report the GPE that woke the system to the kernel
coreboot needs to keep track of the first GPE wake source and
save it in NVS so it can be returned in \_GPE._SWS method.
This is similar to the saving of PM1 status but needs to go
through all the GPE0_STS registers and check for enabled and
triggered events.
A bit of cleanup is done for areas that were touched:
- platform.asl was not formatted correctly
BUG=chrome-os-partner:8127
BRANCH=samus,auron
TEST=manual:
- suspend/resume and wake from EC event like keyboard:
ACPI _SWS is PM1 Index -1 GPE Index 112 ("special" GPIO27)
- suspend/resume and wake from RTC event:
ACPI _SWS is PM1 Index 10 GPE Index -1 (RTC)
- suspend/resume and wake from power button:
ACPI _SWS is PM1 Index 8 GPE Index -1
- suspend/resume and wake from touchpad:
ACPI _SWS is PM1 Index -1 GPE Index 13
- suspend/resume and wake from WLAN:
ACPI _SWS is PM1 Index -1 GPE Index 10
Change-Id: I574f8cd83c8bb42f420e1a00e71a23aa23195f53
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: d4e06c7dfc73f2952ce8f81263e316980aa9760f
Original-Change-Id: I9bfbbe4385f2acc2a50f41ae321b4bae262b7078
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/220324
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9460
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/broadwell/ramstage.c')
-rw-r--r-- | src/soc/intel/broadwell/ramstage.c | 33 |
1 files changed, 28 insertions, 5 deletions
diff --git a/src/soc/intel/broadwell/ramstage.c b/src/soc/intel/broadwell/ramstage.c index beabded070..c9a422f8e4 100644 --- a/src/soc/intel/broadwell/ramstage.c +++ b/src/soc/intel/broadwell/ramstage.c @@ -28,11 +28,12 @@ #include <soc/ramstage.h> #include <soc/intel/broadwell/chip.h> -/* Save bit index for first enabled event in PM1_STS for \_SB._SWS */ -static void s3_save_acpi_wake_source(global_nvs_t *gnvs) +/* Save bit index for PM1_STS and GPE_STS for ACPI _SWS */ +static void save_acpi_wake_source(global_nvs_t *gnvs) { struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); uint16_t pm1; + int gpe_reg; if (!ps) return; @@ -50,8 +51,30 @@ static void s3_save_acpi_wake_source(global_nvs_t *gnvs) if (gnvs->pm1i >= 16) gnvs->pm1i = -1; - printk(BIOS_DEBUG, "ACPI System Wake Source is PM1 Index %d\n", - gnvs->pm1i); + /* Scan for first set bit in GPE registers */ + for (gpe_reg = 0; gpe_reg < GPE0_REG_MAX; gpe_reg++) { + u32 gpe = ps->gpe0_sts[gpe_reg] & ps->gpe0_en[gpe_reg]; + int start = gpe_reg * GPE0_REG_SIZE; + int end = start + GPE0_REG_SIZE; + + if (gpe == 0) { + gnvs->gpei = end; + continue; + } + + for (gnvs->gpei = start; gnvs->gpei < end; gnvs->gpei++) { + if (gpe & 1) + break; + gpe >>= 1; + } + } + + /* If unable to determine then return -1 */ + if (gnvs->gpei >= (GPE0_REG_MAX * GPE0_REG_SIZE)) + gnvs->gpei = -1; + + printk(BIOS_DEBUG, "ACPI _SWS is PM1 Index %d GPE Index %d\n", + gnvs->pm1i, gnvs->gpei); } static void s3_resume_prepare(void) @@ -65,7 +88,7 @@ static void s3_resume_prepare(void) if (!acpi_is_wakeup_s3()) memset(gnvs, 0, sizeof(global_nvs_t)); else - s3_save_acpi_wake_source(gnvs); + save_acpi_wake_source(gnvs); } void broadwell_init_pre_device(void *chip_info) |