diff options
author | Angel Pons <th3fanbus@gmail.com> | 2020-10-26 00:32:42 +0100 |
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committer | Michael Niewöhner <foss@mniewoehner.de> | 2020-11-13 13:23:33 +0000 |
commit | 1500dd081b386db9b03ff78e74831cf6c9f88ba7 (patch) | |
tree | cf6bfb7aa57e70d128ceaa3625cbe9782373d3b3 /src/soc/intel/broadwell/romstage.c | |
parent | 3bd017356a7766c4884e55a28ca481c8a9110ceb (diff) | |
download | coreboot-1500dd081b386db9b03ff78e74831cf6c9f88ba7.tar.xz |
soc/intel/broadwell: Flatten northbridge folder structure
Having folders for bootblock and romstage is no longer necessary.
Change-Id: I7d1f4063de6a1a1ff9ee7478e94f889a50102054
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46795
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/broadwell/romstage.c')
-rw-r--r-- | src/soc/intel/broadwell/romstage.c | 67 |
1 files changed, 67 insertions, 0 deletions
diff --git a/src/soc/intel/broadwell/romstage.c b/src/soc/intel/broadwell/romstage.c new file mode 100644 index 0000000000..2e5db76ce9 --- /dev/null +++ b/src/soc/intel/broadwell/romstage.c @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <arch/romstage.h> +#include <console/console.h> +#include <elog.h> +#include <romstage_handoff.h> +#include <soc/gpio.h> +#include <soc/me.h> +#include <soc/pei_data.h> +#include <soc/pm.h> +#include <soc/romstage.h> +#include <stdint.h> +#include <timestamp.h> + +/* Entry from cpu/intel/car/romstage.c. */ +void mainboard_romstage_entry(void) +{ + struct romstage_params rp = { 0 }; + + post_code(0x30); + + /* System Agent Early Initialization */ + systemagent_early_init(); + + /* PCH Early Initialization */ + pch_early_init(); + + /* Get power state */ + rp.power_state = fill_power_state(); + + elog_boot_notify(rp.power_state->prev_sleep_state == ACPI_S3); + + /* Print useful platform information */ + report_platform_info(); + + /* Set CPU frequency to maximum */ + set_max_freq(); + + /* Initialize GPIOs */ + init_gpios(mainboard_gpio_config); + + /* Fill in mainboard pei_date. */ + mainboard_pre_raminit(&rp); + + post_code(0x32); + + timestamp_add_now(TS_BEFORE_INITRAM); + + rp.pei_data.boot_mode = rp.power_state->prev_sleep_state; + + /* Print ME state before MRC */ + intel_me_status(); + + /* Save ME HSIO version */ + intel_me_hsio_version(&rp.power_state->hsio_version, + &rp.power_state->hsio_checksum); + + /* Initialize RAM */ + raminit(&rp.pei_data); + + timestamp_add_now(TS_AFTER_INITRAM); + + romstage_handoff_init(rp.power_state->prev_sleep_state == ACPI_S3); + + mainboard_post_raminit(&rp); +} |