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| author | Aaron Durbin <adurbin@chromium.org> | 2016-07-13 23:21:41 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-07-15 08:32:49 +0200 |
| commit | 9e6d143a82a852ddfa64f20ceb8695939c1dace1 (patch) | |
| tree | 147ee77b05213ace8941dbebe360df972f026517 /src/soc/intel/broadwell/romstage/power_state.c | |
| parent | c159bb0d76af801bca405e729c5f4b97a18a5a1d (diff) | |
| download | coreboot-9e6d143a82a852ddfa64f20ceb8695939c1dace1.tar.xz | |
soc/intel/broadwell: use common Intel ACPI hardware definitions
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.
BUG=chrome-os-partner:54977
Change-Id: I99d909ee72c3abebb1e9c8ebf44137465264bf0d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15673
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/broadwell/romstage/power_state.c')
| -rw-r--r-- | src/soc/intel/broadwell/romstage/power_state.c | 17 |
1 files changed, 8 insertions, 9 deletions
diff --git a/src/soc/intel/broadwell/romstage/power_state.c b/src/soc/intel/broadwell/romstage/power_state.c index 38a4109a22..cfb24182c1 100644 --- a/src/soc/intel/broadwell/romstage/power_state.c +++ b/src/soc/intel/broadwell/romstage/power_state.c @@ -52,17 +52,16 @@ ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state) static int prev_sleep_state(struct chipset_power_state *ps) { /* Default to S0. */ - int prev_sleep_state = SLEEP_STATE_S0; + int prev_sleep_state = ACPI_S0; if (ps->pm1_sts & WAK_STS) { - switch ((ps->pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) { -#if CONFIG_HAVE_ACPI_RESUME - case SLP_TYP_S3: - prev_sleep_state = SLEEP_STATE_S3; + switch (acpi_sleep_from_pm1(ps->pm1_cnt)) { + case ACPI_S3: + if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) + prev_sleep_state = ACPI_S3; break; -#endif - case SLP_TYP_S5: - prev_sleep_state = SLEEP_STATE_S5; + case ACPI_S5: + prev_sleep_state = ACPI_S5; break; } /* Clear SLP_TYP. */ @@ -70,7 +69,7 @@ static int prev_sleep_state(struct chipset_power_state *ps) } if (ps->gen_pmcon3 & (PWR_FLR | SUS_PWR_FLR)) - prev_sleep_state = SLEEP_STATE_S5; + prev_sleep_state = ACPI_S5; return prev_sleep_state; } |