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authorAaron Durbin <adurbin@chromium.org>2017-12-15 12:26:40 -0700
committerAaron Durbin <adurbin@chromium.org>2017-12-17 18:29:41 +0000
commitdecd062875c1e33d4c9203c2edc0652792a46e73 (patch)
tree83da2b2b82f3e0b5298f89ed2477637ec0766a16 /src/soc/intel/broadwell/romstage/raminit.c
parent934f433d87df0440294be6fc2e6395e0139a5e34 (diff)
downloadcoreboot-decd062875c1e33d4c9203c2edc0652792a46e73.tar.xz
drivers/mrc_cache: move mrc_cache support to drivers
There's nothing intel-specific about the current mrc_cache support. It's logic manages saving non-volatile areas into the boot media. Therefore, expose it to the rest of the system for any and all to use. BUG=b:69614064 Change-Id: I3b331c82a102f88912a3e10507a70207fb20aecc Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/broadwell/romstage/raminit.c')
-rw-r--r--src/soc/intel/broadwell/romstage/raminit.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c
index 0470beec7e..665dad277e 100644
--- a/src/soc/intel/broadwell/romstage/raminit.c
+++ b/src/soc/intel/broadwell/romstage/raminit.c
@@ -21,13 +21,13 @@
#include <console/console.h>
#include <device/pci_def.h>
#include <lib.h>
+#include <mrc_cache.h>
#include <string.h>
#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
#include <ec/google/chromeec/ec.h>
#include <ec/google/chromeec/ec_commands.h>
#endif
#include <vendorcode/google/chromeos/chromeos.h>
-#include <soc/intel/common/mrc_cache.h>
#include <soc/iomap.h>
#include <soc/pei_data.h>
#include <soc/pei_wrapper.h>