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authorElyes HAOUAS <ehaouas@noos.fr>2016-07-29 18:31:16 +0200
committerMartin Roth <martinroth@google.com>2016-07-31 19:27:53 +0200
commit038e7247dc9705ff2d47dd90ec9a807f6feb52ba (patch)
tree8cca6a6db31d20a8e045ee5892e8f9cb8de43f8d /src/soc/intel/broadwell/romstage/stack.c
parentf9e7d1b0ca7282a0d51313a68f90e9298c0c46c6 (diff)
downloadcoreboot-038e7247dc9705ff2d47dd90ec9a807f6feb52ba.tar.xz
src/soc: Capitalize CPU, ACPI, RAM and ROM
Change-Id: I7f0d3400126d593bad8e78f95e6b9a378463b4ce Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15963 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/broadwell/romstage/stack.c')
-rw-r--r--src/soc/intel/broadwell/romstage/stack.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/broadwell/romstage/stack.c b/src/soc/intel/broadwell/romstage/stack.c
index 76307cfbb5..86a1c02b15 100644
--- a/src/soc/intel/broadwell/romstage/stack.c
+++ b/src/soc/intel/broadwell/romstage/stack.c
@@ -78,7 +78,7 @@ void *setup_stack_and_mttrs(void)
num_mtrrs++;
top_of_ram = (uint32_t)cbmem_top();
- /* Cache 8MiB below the top of ram. The top of ram under 4GiB is the
+ /* Cache 8MiB below the top of ram. The top of RAM under 4GiB is the
* start of the TSEG region. It is required to be 8MiB aligned. Set
* this area as cacheable so it can be used later for ramstage before
* setting up the entire RAM as cacheable. */
@@ -88,7 +88,7 @@ void *setup_stack_and_mttrs(void)
slot = stack_push(slot, (top_of_ram - (8 << 20)) | MTRR_TYPE_WRBACK);
num_mtrrs++;
- /* Cache 8MiB at the top of ram. Top of ram is where the TSEG
+ /* Cache 8MiB at the top of ram. Top of RAM is where the TSEG
* region resides. However, it is not restricted to SMM mode until
* SMM has been relocated. By setting the region to cacheable it
* provides faster access when relocating the SMM handler as well