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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2013-07-26 08:53:59 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-12-06 20:45:22 +0100 |
| commit | 48c389e69ebb3922594ccdd4664e7645d399920a (patch) | |
| tree | ebae3bc4498102ead65928528e9378decc075b3e /src/soc/intel/broadwell/romstage | |
| parent | 154768b902384bc53d30eefa83f89e79eaf4ec2f (diff) | |
| download | coreboot-48c389e69ebb3922594ccdd4664e7645d399920a.tar.xz | |
PCI ops: Define read-modify-write routines globally
Change-Id: I7d64f46bb4ec3229879a60159efc8a8408512acd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17690
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/broadwell/romstage')
| -rw-r--r-- | src/soc/intel/broadwell/romstage/pch.c | 16 |
1 files changed, 3 insertions, 13 deletions
diff --git a/src/soc/intel/broadwell/romstage/pch.c b/src/soc/intel/broadwell/romstage/pch.c index 74d31254cb..35a361ae4f 100644 --- a/src/soc/intel/broadwell/romstage/pch.c +++ b/src/soc/intel/broadwell/romstage/pch.c @@ -131,16 +131,6 @@ static void pch_enable_lpc(void) pci_write_config32(PCH_DEV_LPC, LPC_GEN4_DEC, config->gen4_dec); } -static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or) -{ - u32 reg32; - - reg32 = pci_read_config32(dev, reg); - reg32 &= mask; - reg32 |= or; - pci_write_config32(dev, reg, reg32); -} - void pch_early_init(void) { reg_script_run_on_dev(PCH_DEV_LPC, pch_early_init_script); @@ -151,7 +141,7 @@ void pch_early_init(void) enable_smbus(); /* 8.14 Additional PCI Express Programming Steps, step #1 */ - pcie_update_cfg(_PCH_DEV(PCIE, 0), 0xf4, ~0x60, 0); - pcie_update_cfg(_PCH_DEV(PCIE, 0), 0xf4, ~0x80, 0x80); - pcie_update_cfg(_PCH_DEV(PCIE, 0), 0xe2, ~0x30, 0x30); + pci_update_config32(_PCH_DEV(PCIE, 0), 0xf4, ~0x60, 0); + pci_update_config32(_PCH_DEV(PCIE, 0), 0xf4, ~0x80, 0x80); + pci_update_config32(_PCH_DEV(PCIE, 0), 0xe2, ~0x30, 0x30); } |