soc/intel/broadwell: Move PCH code into pch subdir

Change-Id: Icb57eb89b4f225298e43ae27970dc1e27fb6e222
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46706
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

4 files changed, 0 insertions, 260 deletions

diff --git a/src/soc/intel/broadwell/romstage/Makefile.inc b/src/soc/intel/broadwell/romstage/Makefile.inc
index edfec30fdc..b77e7a579d 100644
--- a/src/soc/intel/broadwell/romstage/Makefile.inc
+++ b/src/soc/intel/broadwell/romstage/Makefile.inc
@@ -1,9 +1,6 @@
 romstage-y += ../../../../cpu/intel/car/romstage.c
 romstage-y += cpu.c
-romstage-y += pch.c
-romstage-y += power_state.c
 romstage-y += raminit.c
 romstage-y += report_platform.c
 romstage-y += romstage.c
 romstage-y += systemagent.c
-romstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c
diff --git a/src/soc/intel/broadwell/romstage/pch.c b/src/soc/intel/broadwell/romstage/pch.c
deleted file mode 100644
index 149dda1ca0..0000000000
--- a/src/soc/intel/broadwell/romstage/pch.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <device/device.h>
-#include <device/pci_def.h>
-#include <device/pci_ops.h>
-#include <device/smbus_host.h>
-#include <soc/iomap.h>
-#include <soc/lpc.h>
-#include <soc/pch.h>
-#include <soc/pci_devs.h>
-#include <soc/pm.h>
-#include <soc/rcba.h>
-#include <soc/romstage.h>
-#include <soc/smbus.h>
-#include <soc/intel/broadwell/pch/chip.h>
-
-static void pch_route_interrupts(void)
-{
-	/*
-	 *             GFX    INTA -> PIRQA (MSI)
-	 * D28IP_P1IP  PCIE   INTA -> PIRQA
-	 * D29IP_E1P   EHCI   INTA -> PIRQD
-	 * D20IP_XHCI  XHCI   INTA -> PIRQC (MSI)
-	 * D31IP_SIP   SATA   INTA -> PIRQF (MSI)
-	 * D31IP_SMIP  SMBUS  INTB -> PIRQG
-	 * D31IP_TTIP  THRT   INTC -> PIRQA
-	 * D27IP_ZIP   HDA    INTA -> PIRQG (MSI)
-	 */
-
-	/* Device interrupt pin register (board specific) */
-	RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
-			(INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
-	RCBA32(D29IP) = (INTA << D29IP_E1P);
-	RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) |
-			(INTB << D28IP_P4IP);
-	RCBA32(D27IP) = (INTA << D27IP_ZIP);
-	RCBA32(D26IP) = (INTA << D26IP_E2P);
-	RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
-	RCBA32(D20IP) = (INTA << D20IP_XHCI);
-
-	/* Device interrupt route registers */
-	RCBA32(D31IR) = DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA);	/* LPC */
-	RCBA32(D29IR) = DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD);	/* EHCI */
-	RCBA32(D28IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD);	/* PCIE */
-	RCBA32(D27IR) = DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG);	/* HDA */
-	RCBA32(D23IR) = DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH);	/* SDIO */
-	RCBA32(D22IR) = DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA);	/* ME */
-	RCBA32(D21IR) = DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF);	/* SIO */
-	RCBA32(D20IR) = DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC);	/* XHCI */
-}
-
-static void pch_enable_lpc(void)
-{
-	/* Lookup device tree in romstage */
-	const struct device *const dev = pcidev_on_root(0x1f, 0);
-
-	const struct soc_intel_broadwell_pch_config *config = config_of(dev);
-
-	pci_write_config32(PCH_DEV_LPC, LPC_GEN1_DEC, config->gen1_dec);
-	pci_write_config32(PCH_DEV_LPC, LPC_GEN2_DEC, config->gen2_dec);
-	pci_write_config32(PCH_DEV_LPC, LPC_GEN3_DEC, config->gen3_dec);
-	pci_write_config32(PCH_DEV_LPC, LPC_GEN4_DEC, config->gen4_dec);
-}
-
-void pch_early_init(void)
-{
-	pch_route_interrupts();
-
-	pch_enable_lpc();
-
-	enable_smbus();
-
-	/* 8.14 Additional PCI Express Programming Steps, step #1 */
-	pci_update_config32(_PCH_DEV(PCIE, 0), 0xf4, ~0x60, 0);
-	pci_update_config32(_PCH_DEV(PCIE, 0), 0xf4, ~0x80, 0x80);
-	pci_update_config32(_PCH_DEV(PCIE, 0), 0xe2, ~0x30, 0x30);
-}
diff --git a/src/soc/intel/broadwell/romstage/power_state.c b/src/soc/intel/broadwell/romstage/power_state.c
deleted file mode 100644
index cb1d3e5b9c..0000000000
--- a/src/soc/intel/broadwell/romstage/power_state.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <arch/io.h>
-#include <device/pci_ops.h>
-#include <cbmem.h>
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_def.h>
-#include <string.h>
-#include <soc/iomap.h>
-#include <soc/lpc.h>
-#include <soc/pci_devs.h>
-#include <soc/pm.h>
-#include <soc/romstage.h>
-
-static struct chipset_power_state power_state;
-
-static void migrate_power_state(int is_recovery)
-{
-	struct chipset_power_state *ps_cbmem;
-	struct chipset_power_state *ps_car;
-
-	ps_car = &power_state;
-	ps_cbmem = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*ps_cbmem));
-
-	if (ps_cbmem == NULL) {
-		printk(BIOS_DEBUG, "Not adding power state to cbmem!\n");
-		return;
-	}
-	memcpy(ps_cbmem, ps_car, sizeof(*ps_cbmem));
-}
-ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state)
-
-/* Return 0, 3, or 5 to indicate the previous sleep state. */
-static int prev_sleep_state(struct chipset_power_state *ps)
-{
-	/* Default to S0. */
-	int prev_sleep_state = ACPI_S0;
-
-	if (ps->pm1_sts & WAK_STS) {
-		switch (acpi_sleep_from_pm1(ps->pm1_cnt)) {
-		case ACPI_S3:
-			if (CONFIG(HAVE_ACPI_RESUME))
-				prev_sleep_state = ACPI_S3;
-			break;
-		case ACPI_S5:
-			prev_sleep_state = ACPI_S5;
-			break;
-		}
-		/* Clear SLP_TYP. */
-		outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT);
-	}
-
-	if (ps->gen_pmcon3 & (PWR_FLR | SUS_PWR_FLR))
-		prev_sleep_state = ACPI_S5;
-
-	return prev_sleep_state;
-}
-
-static void dump_power_state(struct chipset_power_state *ps)
-{
-	printk(BIOS_DEBUG, "PM1_STS:   %04x\n", ps->pm1_sts);
-	printk(BIOS_DEBUG, "PM1_EN:    %04x\n", ps->pm1_en);
-	printk(BIOS_DEBUG, "PM1_CNT:   %08x\n", ps->pm1_cnt);
-	printk(BIOS_DEBUG, "TCO_STS:   %04x %04x\n",
-	       ps->tco1_sts, ps->tco2_sts);
-
-	printk(BIOS_DEBUG, "GPE0_STS:  %08x %08x %08x %08x\n",
-	       ps->gpe0_sts[0], ps->gpe0_sts[1],
-	       ps->gpe0_sts[2], ps->gpe0_sts[3]);
-	printk(BIOS_DEBUG, "GPE0_EN:   %08x %08x %08x %08x\n",
-	       ps->gpe0_en[0], ps->gpe0_en[1],
-	       ps->gpe0_en[2], ps->gpe0_en[3]);
-
-	printk(BIOS_DEBUG, "GEN_PMCON: %04x %04x %04x\n",
-	       ps->gen_pmcon1, ps->gen_pmcon2, ps->gen_pmcon3);
-
-	printk(BIOS_DEBUG, "Previous Sleep State: S%d\n",
-	       ps->prev_sleep_state);
-}
-
-/* Fill power state structure from ACPI PM registers */
-struct chipset_power_state *fill_power_state(void)
-{
-	struct chipset_power_state *ps = &power_state;
-
-	ps->pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);
-	ps->pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN);
-	ps->pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
-	ps->tco1_sts = inw(ACPI_BASE_ADDRESS + TCO1_STS);
-	ps->tco2_sts = inw(ACPI_BASE_ADDRESS + TCO2_STS);
-	ps->gpe0_sts[0] = inl(ACPI_BASE_ADDRESS + GPE0_STS(0));
-	ps->gpe0_sts[1] = inl(ACPI_BASE_ADDRESS + GPE0_STS(1));
-	ps->gpe0_sts[2] = inl(ACPI_BASE_ADDRESS + GPE0_STS(2));
-	ps->gpe0_sts[3] = inl(ACPI_BASE_ADDRESS + GPE0_STS(3));
-	ps->gpe0_en[0] = inl(ACPI_BASE_ADDRESS + GPE0_EN(0));
-	ps->gpe0_en[1] = inl(ACPI_BASE_ADDRESS + GPE0_EN(1));
-	ps->gpe0_en[2] = inl(ACPI_BASE_ADDRESS + GPE0_EN(2));
-	ps->gpe0_en[3] = inl(ACPI_BASE_ADDRESS + GPE0_EN(3));
-
-	ps->gen_pmcon1 = pci_read_config16(PCH_DEV_LPC, GEN_PMCON_1);
-	ps->gen_pmcon2 = pci_read_config16(PCH_DEV_LPC, GEN_PMCON_2);
-	ps->gen_pmcon3 = pci_read_config16(PCH_DEV_LPC, GEN_PMCON_3);
-
-	ps->prev_sleep_state = prev_sleep_state(ps);
-
-	dump_power_state(ps);
-
-	return ps;
-}
diff --git a/src/soc/intel/broadwell/romstage/uart.c b/src/soc/intel/broadwell/romstage/uart.c
deleted file mode 100644
index 6b0da2d65c..0000000000
--- a/src/soc/intel/broadwell/romstage/uart.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <device/pci_def.h>
-#include <reg_script.h>
-#include <stdint.h>
-#include <uart8250.h>
-#include <soc/iobp.h>
-#include <soc/serialio.h>
-
-const struct reg_script uart_init[] = {
-	/* Set MMIO BAR */
-	REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, CONFIG_TTYS0_BASE),
-	/* Enable Memory access and Bus Master */
-	REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER),
-	/* Initialize LTR */
-	REG_MMIO_RMW32(CONFIG_TTYS0_BASE + SIO_REG_PPR_GEN,
-		      ~SIO_REG_PPR_GEN_LTR_MODE_MASK, 0),
-	REG_MMIO_RMW32(CONFIG_TTYS0_BASE + SIO_REG_PPR_RST,
-		      ~(SIO_REG_PPR_RST_ASSERT), 0),
-	/* Take UART out of reset */
-	REG_MMIO_OR32(CONFIG_TTYS0_BASE + SIO_REG_PPR_RST,
-		     SIO_REG_PPR_RST_ASSERT),
-	/* Set M and N divisor inputs and enable clock */
-	REG_MMIO_WRITE32(CONFIG_TTYS0_BASE + SIO_REG_PPR_CLOCK,
-			SIO_REG_PPR_CLOCK_EN | SIO_REG_PPR_CLOCK_UPDATE |
-			(SIO_REG_PPR_CLOCK_N_DIV << 16) |
-			(SIO_REG_PPR_CLOCK_M_DIV << 1)),
-	REG_SCRIPT_END
-};
-
-void pch_uart_init(void)
-{
-	/* Program IOBP CB000154h[12,9:8,4:0] = 1001100011111b */
-	u32 gpiodf = 0x131f;
-#if defined(__SIMPLE_DEVICE__)
-	pci_devfn_t dev;
-#else
-	struct device *dev;
-#endif
-
-	/* Put UART in byte access mode for 16550 compatibility */
-	switch (CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER) {
-	case 0:
-		dev = PCH_DEV_UART0;
-		gpiodf |= SIO_IOBP_GPIODF_UART0_BYTE_ACCESS;
-		break;
-	case 1:
-		dev = PCH_DEV_UART1;
-		gpiodf |= SIO_IOBP_GPIODF_UART1_BYTE_ACCESS;
-		break;
-	default:
-		return;
-	}
-
-	/* Program IOBP GPIODF */
-	pch_iobp_update(SIO_IOBP_GPIODF, ~gpiodf, gpiodf);
-
-	/* Program IOBP CB000180h[5:0] = 111111b (undefined register) */
-	pch_iobp_update(0xcb000180, ~0x0000003f, 0x0000003f);
-
-	/* Initialize chipset uart interface */
-	reg_script_run_on_dev(dev, uart_init);
-
-	/*
-	 * Perform standard UART initialization
-	 * Divisor 1 is 115200 BAUD
-	 */
-	uart8250_mem_init(CONFIG_TTYS0_BASE, 1);
-}