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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-12-18 10:24:55 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-07 10:27:32 +0000 |
| commit | f212cf3506a9ad3d699a4afe148bfd554932f7b8 (patch) | |
| tree | 86f810f53d78c9f1e368f4e75d3991158cec2fcf /src/soc/intel/broadwell/smmrelocate.c | |
| parent | 844eda0f3b69e8b724fdf14fc663f808f686037f (diff) | |
| download | coreboot-f212cf3506a9ad3d699a4afe148bfd554932f7b8.tar.xz | |
soc/intel: Standardize names of common MSRs
Use defined name in Intel 64 and IA-32 Architectures Software
Developer’s Manual.
Renamed MSRs are (register address, register name):
0x35 MSR_CORE_THREAD_COUNT
0x121 MSR_EMULATE_PM_TIMER
0x1f4 MSR_PRMRR_PHYS_BASE
0x1f5 MSR_PRMRR_PHYS_MASK
0x2f4 MSR_UNCORE_PRMRR_PHYS_BASE
0x2f5 MSR_UNCORE_PRMRR_PHYS_MASK
Change-Id: I53f11a2ce831456d598aa21303a817d18ac89bba
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Diffstat (limited to 'src/soc/intel/broadwell/smmrelocate.c')
| -rw-r--r-- | src/soc/intel/broadwell/smmrelocate.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c index 5e95bb4693..49b8554f59 100644 --- a/src/soc/intel/broadwell/smmrelocate.c +++ b/src/soc/intel/broadwell/smmrelocate.c @@ -45,8 +45,8 @@ static inline void write_emrr(struct smm_relocation_params *relo_params) { printk(BIOS_DEBUG, "Writing EMRR. base = 0x%08x, mask=0x%08x\n", relo_params->emrr_base.lo, relo_params->emrr_mask.lo); - wrmsr(EMRRphysBase_MSR, relo_params->emrr_base); - wrmsr(EMRRphysMask_MSR, relo_params->emrr_mask); + wrmsr(MSR_PRMRR_PHYS_BASE, relo_params->emrr_base); + wrmsr(MSR_PRMRR_PHYS_MASK, relo_params->emrr_mask); } static inline void write_uncore_emrr(struct smm_relocation_params *relo_params) @@ -55,8 +55,8 @@ static inline void write_uncore_emrr(struct smm_relocation_params *relo_params) "Writing UNCORE_EMRR. base = 0x%08x, mask=0x%08x\n", relo_params->uncore_emrr_base.lo, relo_params->uncore_emrr_mask.lo); - wrmsr(UNCORE_EMRRphysBase_MSR, relo_params->uncore_emrr_base); - wrmsr(UNCORE_EMRRphysMask_MSR, relo_params->uncore_emrr_mask); + wrmsr(MSR_UNCORE_PRMRR_PHYS_BASE, relo_params->uncore_emrr_base); + wrmsr(MSR_UNCORE_PRMRR_PHYS_MASK, relo_params->uncore_emrr_mask); } static void update_save_state(int cpu, uintptr_t curr_smbase, |