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authorMarc Jones <marc.jones@se-eng.com>2014-12-26 22:11:14 -0700
committerMarc Jones <marc.jones@se-eng.com>2014-12-31 21:22:24 +0100
commita6354a1acadc7825364c6a6e7fd3b24a405a62a1 (patch)
treec947844cc6568280240c8bdc225fa581b1ea23af /src/soc/intel/broadwell/spi.c
parentdffd892e47bb8bbfb920447275a2d6b00be904ce (diff)
downloadcoreboot-a6354a1acadc7825364c6a6e7fd3b24a405a62a1.tar.xz
broadwell: Preparations for building
Updated Intel Broadwell for differences in the source based on the chromium tree. It is missing most of the recent updates on coreboot.org. - makefile changes for Elog and IDF tool - kconfig changes for ME, ucode, and other updates - update oprom flag - update timestamp mechanism - cbfs payload function is now generic Change-Id: I82bd0792e9dcf81085246873164de6600528d6fe Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7939 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
Diffstat (limited to 'src/soc/intel/broadwell/spi.c')
-rw-r--r--src/soc/intel/broadwell/spi.c10
1 files changed, 7 insertions, 3 deletions
diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c
index 935c53215e..eeffda0378 100644
--- a/src/soc/intel/broadwell/spi.c
+++ b/src/soc/intel/broadwell/spi.c
@@ -30,8 +30,6 @@
#include <spi-generic.h>
#include <broadwell/pci_devs.h>
-#define min(a, b) ((a)<(b)?(a):(b))
-
#ifdef __SMM__
#define pci_read_config_byte(dev, reg, targ)\
*(targ) = pci_read_config8(dev, reg)
@@ -488,6 +486,11 @@ static int ich_status_poll(u16 bitmask, int wait_til_set)
return -1;
}
+unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len)
+{
+ return min(cntlr.databytes, buf_len);
+}
+
int spi_xfer(struct spi_slave *slave, const void *dout,
unsigned int bytesout, void *din, unsigned int bytesin)
{
@@ -588,7 +591,8 @@ int spi_xfer(struct spi_slave *slave, const void *dout,
while (trans.bytesout || trans.bytesin) {
uint32_t data_length;
- /* SPI addresses are 24 bit only */http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/pentium-n3520-j2850-celeron-n2920-n2820-n2815-n2806-j1850-j1750-datasheet.pdf
+ /* SPI addresses are 24 bit only */
+ /* http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/pentium-n3520-j2850-celeron-n2920-n2820-n2815-n2806-j1850-j1750-datasheet.pdf */
writel_(trans.offset & 0x00FFFFFF, cntlr.addr);
if (trans.bytesout)