diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2017-03-17 10:56:08 -0700 |
|---|---|---|
| committer | Lee Leahy <leroy.p.leahy@intel.com> | 2017-03-17 19:21:53 +0100 |
| commit | 6ef5192627b07662e641feb5049f4183edde9105 (patch) | |
| tree | a8a07245b7e93a90abeb3da9a63b022730ce8a7c /src/soc/intel/broadwell/spi.c | |
| parent | 8a9c7dc08712e71bec5bc92bbaf93bf43126cd0d (diff) | |
| download | coreboot-6ef5192627b07662e641feb5049f4183edde9105.tar.xz | |
soc/intel/broadwell: Fix other issues detected by checkpatch
Fix the following error and warnings detected by checkpatch.pl:
ERROR: switch and case should be at the same indent
WARNING: line over 80 characters
WARNING: storage class should be at the beginning of the declaration
WARNING: adding a line without newline at end of file
WARNING: __func__ should be used instead of gcc specific __FUNCTION__
WARNING: Comparisons should place the constant on the right side of the test
TEST=None
Change-Id: I85c400e4a087996fc81ab8b0e5422ba31df3c982
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18885
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/broadwell/spi.c')
| -rw-r--r-- | src/soc/intel/broadwell/spi.c | 15 |
1 files changed, 10 insertions, 5 deletions
diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c index 22a0dab6e3..aaf3b85b5a 100644 --- a/src/soc/intel/broadwell/spi.c +++ b/src/soc/intel/broadwell/spi.c @@ -421,7 +421,8 @@ static int spi_setup_offset(spi_transaction *trans) spi_use_out(trans, 3); return 1; default: - printk(BIOS_DEBUG, "Unrecognized SPI transaction type %#x\n", trans->type); + printk(BIOS_DEBUG, "Unrecognized SPI transaction type %#x\n", + trans->type); return -1; } } @@ -533,7 +534,8 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, return -1; if (status & SPIS_FCERR) { - printk(BIOS_DEBUG, "ICH SPI: Command transaction error\n"); + printk(BIOS_DEBUG, + "ICH SPI: Command transaction error\n"); return -1; } @@ -548,8 +550,8 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, * by the SPI chip driver. */ if (trans.bytesout > cntlr.databytes) { - printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI chip driver use" - " CONTROLLER_PAGE_LIMIT?\n"); + printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI" + " chip driver use CONTROLLER_PAGE_LIMIT?\n"); return -1; } @@ -561,7 +563,10 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, uint32_t data_length; /* SPI addresses are 24 bit only */ - /* http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/pentium-n3520-j2850-celeron-n2920-n2820-n2815-n2806-j1850-j1750-datasheet.pdf */ + /* http://www.intel.com/content/dam/www/public/us/en/documents/ + * datasheets/pentium-n3520-j2850-celeron-n2920-n2820-n2815- + * n2806-j1850-j1750-datasheet.pdf + */ writel_(trans.offset & 0x00FFFFFF, cntlr.addr); if (trans.bytesout) |