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authorAngel Pons <th3fanbus@gmail.com>2020-07-07 22:08:26 +0200
committerMichael Niewöhner <c0d3z3r0@review.coreboot.org>2020-07-09 21:29:37 +0000
commit6dd466c00219b763e606230ed67686a240f5007e (patch)
tree79a9f4b55dcf49078f5f817943eede0d76568493 /src/soc/intel/broadwell
parent20d7bd0291abafaa73de7424f199e4ada483c0d4 (diff)
downloadcoreboot-6dd466c00219b763e606230ed67686a240f5007e.tar.xz
soc/intel/broadwell/pcie.c: Drop dead code
This code is not even being build-tested. Drop it before it grows moss. Change-Id: Ia314148abc900685d85aede3add480614fa8e99c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Michael Niewöhner
Diffstat (limited to 'src/soc/intel/broadwell')
-rw-r--r--src/soc/intel/broadwell/pcie.c12
1 files changed, 0 insertions, 12 deletions
diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c
index 9eb14d9850..14dcd3f556 100644
--- a/src/soc/intel/broadwell/pcie.c
+++ b/src/soc/intel/broadwell/pcie.c
@@ -590,18 +590,6 @@ static void pch_pcie_init(struct device *dev)
reg16 |= PCI_BRIDGE_CTL_NO_ISA;
pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16);
-#ifdef EVEN_MORE_DEBUG
- u32 reg32;
- reg32 = pci_read_config32(dev, 0x20);
- printk(BIOS_SPEW, " MBL = 0x%08x\n", reg32);
- reg32 = pci_read_config32(dev, 0x24);
- printk(BIOS_SPEW, " PMBL = 0x%08x\n", reg32);
- reg32 = pci_read_config32(dev, 0x28);
- printk(BIOS_SPEW, " PMBU32 = 0x%08x\n", reg32);
- reg32 = pci_read_config32(dev, 0x2c);
- printk(BIOS_SPEW, " PMLU32 = 0x%08x\n", reg32);
-#endif
-
/* Clear errors in status registers */
reg16 = pci_read_config16(dev, 0x06);
pci_write_config16(dev, 0x06, reg16);