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authorMatt DeVillier <matt.devillier@gmail.com>2017-02-16 11:45:19 -0600
committerMartin Roth <martinroth@google.com>2017-02-20 04:44:13 +0100
commitee6a612eb2edb32a55ee92c6fdfcdc474c6b21f1 (patch)
tree58e6ea542f08ca957da9a5462ae0e286d70d2d3a /src/soc/intel/broadwell
parentefd9dee646629948a54f68eca21b6ee922c55e10 (diff)
downloadcoreboot-ee6a612eb2edb32a55ee92c6fdfcdc474c6b21f1.tar.xz
Revert "intel/lynxpoint,broadwell: Fix eDP display in Windows, SeaBios & Tiano"
We've been able to narrow down the problem to a single register/ single bit, so revert this commit and address the problem in a follow-on commit. This reverts commit 0f2025da0fd4dce6b951b4c4b97c9370ca7d66db. Change-Id: I780f9ea2976dd223aaa3e060aef6e1af8012c346 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/18384 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/broadwell')
-rw-r--r--src/soc/intel/broadwell/Kconfig9
-rw-r--r--src/soc/intel/broadwell/lpc.c2
2 files changed, 0 insertions, 11 deletions
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 01bcaf1497..0cbd9e4784 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -208,13 +208,4 @@ config CHIPSET_BOOTBLOCK_INCLUDE
string
default "soc/intel/broadwell/bootblock/timestamp.inc"
-config BROADWELL_POWER_OPTIMIZER
- bool "Enable Power Optimizer"
- default y if CHROMEOS
- help
- Enable the power optimizer for the High Speed I/O
- Power Control (HSIOPC). This can break graphics
- under Windows, but can improve battery life under
- 'mostly idle' conditions.
-
endif
diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c
index e4db498e30..c1600c5370 100644
--- a/src/soc/intel/broadwell/lpc.c
+++ b/src/soc/intel/broadwell/lpc.c
@@ -260,7 +260,6 @@ static const struct reg_script pch_pm_init_script[] = {
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33b4, 0x00007001),
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3350, 0x022ddfff),
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3354, 0x00000001),
-#if IS_ENABLED(CONFIG_BROADWELL_POWER_OPTIMIZER)
/* Power Optimizer */
REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33d4, 0x08000000),
REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33c8, 0x08000080),
@@ -272,7 +271,6 @@ static const struct reg_script pch_pm_init_script[] = {
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a84, 0x00001005),
REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33d4, 0x2fff2fb1),
REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33c8, 0x00008000),
-#endif
REG_SCRIPT_END
};