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| author | Subrata Banik <subrata.banik@intel.com> | 2018-12-10 14:11:35 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2018-12-13 04:32:57 +0000 |
| commit | 53b08c347f54970cf5f6ce35b8e1a1fe5f8a11f9 (patch) | |
| tree | b4eed19fbf1b9f35dfbdddcc43fc84469176ec59 /src/soc/intel/broadwell | |
| parent | e3110b862071ae0797afb0688495315a7dd47739 (diff) | |
| download | coreboot-53b08c347f54970cf5f6ce35b8e1a1fe5f8a11f9.tar.xz | |
cpuid: Add helper function for cpuid(1) functions
This patch introduces 3 helper function for cpuid(1) :
1. cpu_get_cpuid() -> to get processor id (from cpuid.eax)
2. cpu_get_feature_flags_ecx -> to get processor feature flag (from cpuid.ecx)
3. cpu_get_feature_flags_edx -> to get processor feature flag (from cpuid.edx)
Above 3 helper functions are targeted to replace majority of cpuid(1)
references.
Change-Id: Ib96a7c79dadb1feff0b8d58aa408b355fbb3bc50
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/30123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/broadwell')
| -rw-r--r-- | src/soc/intel/broadwell/cpu.c | 7 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/romstage/report_platform.c | 15 |
2 files changed, 12 insertions, 10 deletions
diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index 2f9f78f69e..ec8f7f30a8 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -19,6 +19,7 @@ #include <device/pci.h> #include <string.h> #include <arch/acpi.h> +#include <arch/cpu.h> #include <cpu/cpu.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> @@ -498,12 +499,12 @@ static void enable_lapic_tpr(void) static void configure_dca_cap(void) { - struct cpuid_result cpuid_regs; + uint32_t feature_flag; msr_t msr; /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */ - cpuid_regs = cpuid(1); - if (cpuid_regs.ecx & (1 << 18)) { + feature_flag = cpu_get_feature_flags_ecx(); + if (feature_flag & CPUID_DCA) { msr = rdmsr(IA32_PLATFORM_DCA_CAP); msr.lo |= 1; wrmsr(IA32_PLATFORM_DCA_CAP, msr); diff --git a/src/soc/intel/broadwell/romstage/report_platform.c b/src/soc/intel/broadwell/romstage/report_platform.c index 44a3d2714c..db4b2ebdc5 100644 --- a/src/soc/intel/broadwell/romstage/report_platform.c +++ b/src/soc/intel/broadwell/romstage/report_platform.c @@ -86,7 +86,7 @@ static struct { static void report_cpu_info(void) { struct cpuid_result cpuidr; - u32 i, index; + u32 i, index, cpu_id, cpu_feature_flag; char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */ int vt, txt, aes; msr_t microcode_ver; @@ -114,12 +114,12 @@ static void report_cpu_info(void) microcode_ver.lo = 0; microcode_ver.hi = 0; wrmsr(IA32_BIOS_SIGN_ID, microcode_ver); - cpuidr = cpuid(1); + cpu_id = cpu_get_cpuid(); microcode_ver = rdmsr(IA32_BIOS_SIGN_ID); /* Look for string to match the name */ for (i = 0; i < ARRAY_SIZE(cpu_table); i++) { - if (cpu_table[i].cpuid == cpuidr.eax) { + if (cpu_table[i].cpuid == cpu_id) { cpu_type = cpu_table[i].name; break; } @@ -127,11 +127,12 @@ static void report_cpu_info(void) printk(BIOS_DEBUG, "CPU: %s\n", cpu_name); printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n", - cpuidr.eax, cpu_type, microcode_ver.hi); + cpu_id, cpu_type, microcode_ver.hi); - aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0; - txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0; - vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0; + cpu_feature_flag = cpu_get_feature_flags_ecx(); + aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0; + txt = (cpu_feature_flag & CPUID_SMX) ? 1 : 0; + vt = (cpu_feature_flag & CPUID_VMX) ? 1 : 0; printk(BIOS_DEBUG, "CPU: AES %ssupported, TXT %ssupported, " "VT %ssupported\n", mode[aes], mode[txt], mode[vt]); } |