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author | Julius Werner <jwerner@chromium.org> | 2017-03-16 14:08:09 -0700 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2017-03-17 11:38:22 +0100 |
commit | 2d99f3b15886ff984ae469b50d850b360e19911e (patch) | |
tree | d92e9c0412284e2695663a71a8c57fb88a30ac11 /src/soc/intel/broadwell | |
parent | 336a34c81be7455ce2ec978b31fb04f5d4518ec0 (diff) | |
download | coreboot-2d99f3b15886ff984ae469b50d850b360e19911e.tar.xz |
google/veyron: Work around RAM code strapping error
With a recent patch (google/veyron_*: Add new Micron and Hynix modules)
we switched RAM codes for Veyron boards to tri-state since we were
running out of binary numbers. Unfortunately we only tested that change
on Minnie and Speedy, and it turns out that it broke Jaq, Jerry and
Mighty. The "high" RAM code pins on those boards were incorrectly
strapped with 100Kohm resistors (as opposed to 1Kohm on Minnie and
Speedy), which is too high to overpower the SoC-internal pull-down we
use to differentiate "high" from "tri-state". Since we already used
tri-state codes on some Minnie and Speedy SKUs we have to hack up the
code to work differently on these two groups of boards to keep
everything working.
BRANCH=veyron
BUG=b:36279493
TEST=Compiled, confirmed ram_code called the right function depending on
board.
Change-Id: I253b213ef7ca621ce47a7a55a5119a167d944078
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18859
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/broadwell')
0 files changed, 0 insertions, 0 deletions