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authorDuncan Laurie <dlaurie@chromium.org>2015-09-08 16:10:30 -0700
committerPatrick Georgi <pgeorgi@google.com>2015-09-17 14:46:53 +0000
commit81a4c85acf664156bb68807f681cd40928bf8267 (patch)
tree572dfe450bd0847a99b1428316929530847c6789 /src/soc/intel/broadwell
parente73da80d2c63f14cdc301a2436cf9b93dc5a531f (diff)
downloadcoreboot-81a4c85acf664156bb68807f681cd40928bf8267.tar.xz
broadwell: Switch to using common ACPI _SWS code
Use the common ACPI _SWS code and provide a function to fill out the wake source data. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-samus coreboot Change-Id: I3d2ceca8585314122b78317acb7f848efb6e9a14 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d8afaee8e27222639c5e249d53be28cddcb78f72 Original-Change-Id: Ie551ecf3397c304216046cc2046c071f7b766e5f Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298168 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11647 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/broadwell')
-rw-r--r--src/soc/intel/broadwell/Kconfig1
-rw-r--r--src/soc/intel/broadwell/acpi/platform.asl21
-rw-r--r--src/soc/intel/broadwell/ramstage.c57
3 files changed, 15 insertions, 64 deletions
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index e01d5598ec..6561fe27fa 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -42,6 +42,7 @@ config CPU_SPECIFIC_OPTIONS
select UDELAY_TSC
select SOC_INTEL_COMMON
select HAVE_INTEL_FIRMWARE
+ select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
config BOOTBLOCK_CPU_INIT
string
diff --git a/src/soc/intel/broadwell/acpi/platform.asl b/src/soc/intel/broadwell/acpi/platform.asl
index d302720ccc..c00edeb792 100644
--- a/src/soc/intel/broadwell/acpi/platform.asl
+++ b/src/soc/intel/broadwell/acpi/platform.asl
@@ -18,6 +18,9 @@
* Foundation, Inc.
*/
+/* Enable ACPI _SWS methods */
+#include <soc/intel/common/acpi/acpi_wake_source.asl>
+
/* The APM port can be used for generating software SMIs */
OperationRegion (APMP, SystemIO, 0xb2, 2)
@@ -71,21 +74,3 @@ Method (_WAK, 1)
{
Return (Package (){ 0, 0 })
}
-
-Scope (\_SB)
-{
- Method (_SWS)
- {
- /* Index into PM1 for device that caused wake */
- Return (\PM1I)
- }
-}
-
-Scope (\_GPE)
-{
- Method (_SWS)
- {
- /* Index into GPE for device that caused wake */
- Return (\GPEI)
- }
-}
diff --git a/src/soc/intel/broadwell/ramstage.c b/src/soc/intel/broadwell/ramstage.c
index e699e0233a..c8fb6edbfa 100644
--- a/src/soc/intel/broadwell/ramstage.c
+++ b/src/soc/intel/broadwell/ramstage.c
@@ -27,56 +27,23 @@
#include <soc/pm.h>
#include <soc/ramstage.h>
#include <soc/intel/broadwell/chip.h>
+#include <soc/intel/common/acpi.h>
-/* Save bit index for PM1_STS and GPE_STS for ACPI _SWS */
-static void save_acpi_wake_source(global_nvs_t *gnvs)
+/* Save wake source information for calculating ACPI _SWS values */
+int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0)
{
struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);
- uint16_t pm1;
- int gpe_reg;
+ static uint32_t gpe0_sts[GPE0_REG_MAX];
+ int i;
- if (!ps)
- return;
-
- pm1 = ps->pm1_sts & ps->pm1_en;
-
- /* Scan for first set bit in PM1 */
- for (gnvs->pm1i = 0; gnvs->pm1i < 16; gnvs->pm1i++) {
- if (pm1 & 1)
- break;
- pm1 >>= 1;
- }
-
- /* If unable to determine then return -1 */
- if (gnvs->pm1i >= 16)
- gnvs->pm1i = -1;
-
- /* Scan for first set bit in GPE registers */
- gnvs->gpei = -1;
- for (gpe_reg = 0; gpe_reg < GPE0_REG_MAX; gpe_reg++) {
- u32 gpe = ps->gpe0_sts[gpe_reg] & ps->gpe0_en[gpe_reg];
- int start = gpe_reg * GPE0_REG_SIZE;
- int end = start + GPE0_REG_SIZE;
-
- if (gpe == 0) {
- if (!gnvs->gpei)
- gnvs->gpei = end;
- continue;
- }
-
- for (gnvs->gpei = start; gnvs->gpei < end; gnvs->gpei++) {
- if (gpe & 1)
- break;
- gpe >>= 1;
- }
- }
+ *pm1 = ps->pm1_sts & ps->pm1_en;
- /* If unable to determine then return -1 */
- if (gnvs->gpei >= (GPE0_REG_MAX * GPE0_REG_SIZE))
- gnvs->gpei = -1;
+ /* Mask off GPE0 status bits that are not enabled */
+ *gpe0 = &gpe0_sts[0];
+ for (i = 0; i < GPE0_REG_MAX; i++)
+ gpe0_sts[i] = ps->gpe0_sts[i] & ps->gpe0_en[i];
- printk(BIOS_DEBUG, "ACPI _SWS is PM1 Index %lld GPE Index %lld\n",
- gnvs->pm1i, gnvs->gpei);
+ return GPE0_REG_MAX;
}
static void s3_resume_prepare(void)
@@ -89,8 +56,6 @@ static void s3_resume_prepare(void)
if (!acpi_is_wakeup_s3())
memset(gnvs, 0, sizeof(global_nvs_t));
- else
- save_acpi_wake_source(gnvs);
}
void broadwell_init_pre_device(void *chip_info)