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authorKyösti Mälkki <kyosti.malkki@gmail.com>2016-06-17 07:54:36 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2016-06-18 19:59:38 +0200
commit9d2762ca6f2c0414afdca210ba996db7a0956690 (patch)
tree91083adaa53fae278bbad0f8452de134eb8b6524 /src/soc/intel/broadwell
parente813c15443c90ad09d9182f3cca94937df124847 (diff)
downloadcoreboot-9d2762ca6f2c0414afdca210ba996db7a0956690.tar.xz
intel cache_as_ram: Fix typo in comment
Change-Id: I2539e490e160e01cab2ad8d2086d2f242a88c640 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15223 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/soc/intel/broadwell')
-rw-r--r--src/soc/intel/broadwell/romstage/cache_as_ram.inc2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/broadwell/romstage/cache_as_ram.inc b/src/soc/intel/broadwell/romstage/cache_as_ram.inc
index a636e9f7ad..20ef6e9758 100644
--- a/src/soc/intel/broadwell/romstage/cache_as_ram.inc
+++ b/src/soc/intel/broadwell/romstage/cache_as_ram.inc
@@ -256,7 +256,7 @@ before_romstage:
post_code(0x38)
- /* Setup stack as indicated by return value from ramstage_main(). */
+ /* Setup stack as indicated by return value from romstage_main(). */
movl %ebx, %esp
/* Get number of MTRRs. */