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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-17 20:51:08 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-26 21:08:41 +0000
commitcd7a70f4879ff6e0f3e334ddf1031ccf0c0d31cf (patch)
treeb0438431df0943ab5f0fa9d80a99fc265130ac23 /src/soc/intel/broadwell
parent16248e89ecf73a76e5d9e9e2de46146f7ffece88 (diff)
downloadcoreboot-cd7a70f4879ff6e0f3e334ddf1031ccf0c0d31cf.tar.xz
soc/intel: Use common romstage code
This provides stack guards with checking and common entry into postcar. The code in cpu/intel/car/romstage.c is candidate for becoming architectural so function prototype is moved to <arch/romstage.h>. Change-Id: I4c5a9789e7cf3f7f49a4a33e21dac894320a9639 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34893 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/broadwell')
-rw-r--r--src/soc/intel/broadwell/romstage/romstage.c1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c
index 3f264ff5ec..b3662e1591 100644
--- a/src/soc/intel/broadwell/romstage/romstage.c
+++ b/src/soc/intel/broadwell/romstage/romstage.c
@@ -21,7 +21,6 @@
#include <bootmode.h>
#include <cbmem.h>
#include <console/console.h>
-#include <cpu/intel/romstage.h>
#include <cpu/x86/mtrr.h>
#include <elog.h>
#include <program_loading.h>