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authorMartin Roth <martinroth@google.com>2015-08-18 10:41:54 -0600
committerMartin Roth <martinroth@google.com>2015-08-25 17:36:45 +0000
commitdf205067c976d917563a02fc6ebf1cff329a4097 (patch)
tree325c4cf09361bada19aee32c8fdf009aabd4e641 /src/soc/intel/broadwell
parent1fff0d26f80c9f412a500f40b29bbbd88572febc (diff)
downloadcoreboot-df205067c976d917563a02fc6ebf1cff329a4097.tar.xz
Intel: Remove CACHE_MRC_BIN - 'selected' everywhere in Kconfig
The Kconfig symbol CACHE_MRC_BIN was getting forced enabled everywhere it existed. Remove the Kconfig symbol and get rid of the #if statements surrounding the code. This fixes the Kconfig warning for Haswell & Broadwell chips: warning: (NORTHBRIDGE_INTEL_HASWELL && NORTHBRIDGE_INTEL_SANDYBRIDGE && NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE && NORTHBRIDGE_INTEL_IVYBRIDGE && NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE && CPU_SPECIFIC_OPTIONS) selects CACHE_MRC_BIN which has unmet direct dependencies (CPU_INTEL_SOCKET_RPGA988B || CPU_INTEL_SOCKET_RPGA989) Change-Id: Ie0f0726e3d6f217e2cb3be73034405081ce0735a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11270 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/broadwell')
-rw-r--r--src/soc/intel/broadwell/Kconfig1
-rw-r--r--src/soc/intel/broadwell/romstage/cache_as_ram.inc4
2 files changed, 0 insertions, 5 deletions
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 5853118268..524366c56f 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -14,7 +14,6 @@ config CPU_SPECIFIC_OPTIONS
select VGA_ROM_RUN if !PAYLOAD_SEABIOS
select ALWAYS_LOAD_OPROM if !PAYLOAD_SEABIOS
select BACKUP_DEFAULT_SMM_REGION
- select CACHE_MRC_BIN
select CACHE_MRC_SETTINGS
select MRC_SETTINGS_PROTECT
select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
diff --git a/src/soc/intel/broadwell/romstage/cache_as_ram.inc b/src/soc/intel/broadwell/romstage/cache_as_ram.inc
index 05d4889f3f..3f1b12af18 100644
--- a/src/soc/intel/broadwell/romstage/cache_as_ram.inc
+++ b/src/soc/intel/broadwell/romstage/cache_as_ram.inc
@@ -153,7 +153,6 @@ clear_mtrrs:
wrmsr
post_code(0x27)
-#if CONFIG_CACHE_MRC_BIN
/* Enable caching for ram init code to run faster */
movl $MTRRphysBase_MSR(2), %ecx
movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax
@@ -163,7 +162,6 @@ clear_mtrrs:
movl $(CACHE_MRC_MASK | MTRRphysMaskValid), %eax
movl $CPU_PHYSMASK_HI, %edx
wrmsr
-#endif
post_code(0x28)
/* Enable cache. */
@@ -239,7 +237,6 @@ before_romstage:
andl $~1, %eax
wrmsr
-#if CONFIG_CACHE_MRC_BIN
/* Clear MTRR that was used to cache MRC */
xorl %eax, %eax
xorl %edx, %edx
@@ -247,7 +244,6 @@ before_romstage:
wrmsr
movl $MTRRphysMask_MSR(2), %ecx
wrmsr
-#endif
post_code(0x33)