intel/smm: Provide common smm_relocation_params

Pull in all copies of smm_relocation_params structs defined
for intel platforms.

Pull in all the inlined MSR accessors to the header file.

Change-Id: I39c6cffee95433aea1a3c783b869eedfff094413
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

8 files changed, 0 insertions, 73 deletions

diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c
index 8fe66dce5b..287b5b5532 100644
--- a/src/soc/intel/broadwell/cpu.c
+++ b/src/soc/intel/broadwell/cpu.c
@@ -36,7 +36,6 @@
 #include <soc/pci_devs.h>
 #include <soc/ramstage.h>
 #include <soc/rcba.h>
-#include <soc/smm.h>
 #include <soc/systemagent.h>
 #include <soc/intel/broadwell/chip.h>
 #include <cpu/intel/common/common.h>
diff --git a/src/soc/intel/broadwell/include/soc/smm.h b/src/soc/intel/broadwell/include/soc/smm.h
deleted file mode 100644
index 909294c6e6..0000000000
--- a/src/soc/intel/broadwell/include/soc/smm.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _BROADWELL_SMM_H_
-#define _BROADWELL_SMM_H_
-
-#include <stdint.h>
-#include <cpu/x86/msr.h>
-
-
-struct smm_relocation_params {
-	uintptr_t ied_base;
-	size_t ied_size;
-	msr_t smrr_base;
-	msr_t smrr_mask;
-	msr_t prmrr_base;
-	msr_t prmrr_mask;
-	msr_t uncore_prmrr_base;
-	msr_t uncore_prmrr_mask;
-	/* The smm_save_state_in_msrs field indicates if SMM save state
-	 * locations live in MSRs. This indicates to the CPUs how to adjust
-	 * the SMMBASE and IEDBASE */
-	int smm_save_state_in_msrs;
-};
-
-#endif
diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c
index ad50dd35db..48492d3468 100644
--- a/src/soc/intel/broadwell/memmap.c
+++ b/src/soc/intel/broadwell/memmap.c
@@ -21,7 +21,6 @@
 #include <device/pci_ops.h>
 #include <soc/pci_devs.h>
 #include <soc/systemagent.h>
-#include <soc/smm.h>
 #include <stdint.h>
 
 static uintptr_t dpr_region_start(void)
diff --git a/src/soc/intel/broadwell/pei_data.c b/src/soc/intel/broadwell/pei_data.c
index f745348a7f..09753addb8 100644
--- a/src/soc/intel/broadwell/pei_data.c
+++ b/src/soc/intel/broadwell/pei_data.c
@@ -19,7 +19,6 @@
 #include <soc/iomap.h>
 #include <soc/pei_data.h>
 #include <soc/pei_wrapper.h>
-#include <soc/smm.h>
 
 static void ABI_X86 send_to_console(unsigned char b)
 {
diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c
index c13761df3a..03b564f83a 100644
--- a/src/soc/intel/broadwell/romstage/raminit.c
+++ b/src/soc/intel/broadwell/romstage/raminit.c
@@ -33,7 +33,6 @@
 #include <soc/pei_wrapper.h>
 #include <soc/pm.h>
 #include <soc/romstage.h>
-#include <soc/smm.h>
 #include <soc/systemagent.h>
 
 /*
diff --git a/src/soc/intel/broadwell/smi.c b/src/soc/intel/broadwell/smi.c
index 17196da438..2bdeecc943 100644
--- a/src/soc/intel/broadwell/smi.c
+++ b/src/soc/intel/broadwell/smi.c
@@ -24,7 +24,6 @@
 #include <soc/iomap.h>
 #include <soc/pch.h>
 #include <soc/pm.h>
-#include <soc/smm.h>
 
 void smm_southbridge_clear_state(void)
 {
diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c
index ca99487eb5..c2843a7cc0 100644
--- a/src/soc/intel/broadwell/smihandler.c
+++ b/src/soc/intel/broadwell/smihandler.c
@@ -33,7 +33,6 @@
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
 #include <soc/rcba.h>
-#include <soc/smm.h>
 #include <soc/xhci.h>
 #include <drivers/intel/gma/i915_reg.h>
 
diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c
index 21c534a4c6..b5af9895f9 100644
--- a/src/soc/intel/broadwell/smmrelocate.c
+++ b/src/soc/intel/broadwell/smmrelocate.c
@@ -30,37 +30,8 @@
 #include <soc/cpu.h>
 #include <soc/msr.h>
 #include <soc/pci_devs.h>
-#include <soc/smm.h>
 #include <soc/systemagent.h>
 
-/* This gets filled in and used during relocation. */
-static struct smm_relocation_params smm_reloc_params;
-
-static inline void write_smrr(struct smm_relocation_params *relo_params)
-{
-	printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
-	       relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
-	wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base);
-	wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);
-}
-
-static inline void write_prmrr(struct smm_relocation_params *relo_params)
-{
-	printk(BIOS_DEBUG, "Writing PRMRR. base = 0x%08x, mask=0x%08x\n",
-	       relo_params->prmrr_base.lo, relo_params->prmrr_mask.lo);
-	wrmsr(MSR_PRMRR_PHYS_BASE, relo_params->prmrr_base);
-	wrmsr(MSR_PRMRR_PHYS_MASK, relo_params->prmrr_mask);
-}
-
-static inline void write_uncore_prmrr(struct smm_relocation_params *relo_params)
-{
-	printk(BIOS_DEBUG,
-	       "Writing UNCORE_PRMRR. base = 0x%08x, mask=0x%08x\n",
-	       relo_params->uncore_prmrr_base.lo,
-	       relo_params->uncore_prmrr_mask.lo);
-	wrmsr(MSR_UNCORE_PRMRR_PHYS_BASE, relo_params->uncore_prmrr_base);
-	wrmsr(MSR_UNCORE_PRMRR_PHYS_MASK, relo_params->uncore_prmrr_mask);
-}
 
 static void update_save_state(int cpu, uintptr_t curr_smbase,
 				uintptr_t staggered_smbase,