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authorKyösti Mälkki <kyosti.malkki@gmail.com>2020-01-06 19:41:42 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-01-14 18:18:26 +0000
commitf555a58abc487270d4ba42527b1b43850bd718c0 (patch)
tree5285cf1bb4cc64cedf5c9defa78ea63803aca3e5 /src/soc/intel/broadwell
parent542fa6de384d4b79d8964512b4088bcd90863bd2 (diff)
downloadcoreboot-f555a58abc487270d4ba42527b1b43850bd718c0.tar.xz
sb/intel/common: Declare common smbus_base() and enable_smbus()
This avoids including platform-specific headers with different filenames from common code. Change-Id: Idf9893e55949d63f3ceca2249e618d0f81320321 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/broadwell')
-rw-r--r--src/soc/intel/broadwell/include/soc/romstage.h2
-rw-r--r--src/soc/intel/broadwell/romstage/pch.c1
-rw-r--r--src/soc/intel/broadwell/romstage/smbus.c9
3 files changed, 9 insertions, 3 deletions
diff --git a/src/soc/intel/broadwell/include/soc/romstage.h b/src/soc/intel/broadwell/include/soc/romstage.h
index 46316526b9..b32b043b79 100644
--- a/src/soc/intel/broadwell/include/soc/romstage.h
+++ b/src/soc/intel/broadwell/include/soc/romstage.h
@@ -42,6 +42,4 @@ void pch_early_init(void);
void pch_uart_init(void);
void intel_early_me_status(void);
-void enable_smbus(void);
-
#endif
diff --git a/src/soc/intel/broadwell/romstage/pch.c b/src/soc/intel/broadwell/romstage/pch.c
index af8ea53dea..e8f4eb89ee 100644
--- a/src/soc/intel/broadwell/romstage/pch.c
+++ b/src/soc/intel/broadwell/romstage/pch.c
@@ -16,6 +16,7 @@
#include <device/device.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
+#include <device/smbus_host.h>
#include <reg_script.h>
#include <soc/iomap.h>
#include <soc/lpc.h>
diff --git a/src/soc/intel/broadwell/romstage/smbus.c b/src/soc/intel/broadwell/romstage/smbus.c
index dd5d030302..4b08b4cbcb 100644
--- a/src/soc/intel/broadwell/romstage/smbus.c
+++ b/src/soc/intel/broadwell/romstage/smbus.c
@@ -15,6 +15,7 @@
*/
#include <device/pci_def.h>
+#include <device/smbus_host.h>
#include <reg_script.h>
#include <soc/iomap.h>
#include <soc/pci_devs.h>
@@ -36,7 +37,13 @@ static const struct reg_script smbus_init_script[] = {
REG_SCRIPT_END,
};
-void enable_smbus(void)
+uintptr_t smbus_base(void)
+{
+ return SMBUS_BASE_ADDRESS;
+}
+
+int smbus_enable_iobar(uintptr_t base)
{
reg_script_run_on_dev(PCH_DEV_SMBUS, smbus_init_script);
+ return 0;
}