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| author | Angel Pons <th3fanbus@gmail.com> | 2020-10-13 23:32:55 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-10-23 20:29:28 +0000 |
| commit | 29a52c8308ab270c46c1d859db308ba1de5d1e81 (patch) | |
| tree | 578c14f1dd9ebdb0907ec222a4f873ccdb47c0e3 /src/soc/intel/broadwell | |
| parent | 162a73759901e0292bb7da593c31391bc0230bc0 (diff) | |
| download | coreboot-29a52c8308ab270c46c1d859db308ba1de5d1e81.tar.xz | |
soc/intel/broadwell: Add ECC config reporting
This has been taken from Haswell, and is just to reduce differences.
Change-Id: Ib872cbcd20d6e212b1f55400aa350dc6ba44dc2a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel/broadwell')
| -rw-r--r-- | src/soc/intel/broadwell/romstage/raminit.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c index 65e386a7c7..7020ddfe0d 100644 --- a/src/soc/intel/broadwell/romstage/raminit.c +++ b/src/soc/intel/broadwell/romstage/raminit.c @@ -21,6 +21,13 @@ #include <soc/romstage.h> #include <soc/systemagent.h> +static const char *const ecc_decoder[] = { + "inactive", + "active on IO", + "disabled on IO", + "active", +}; + /* * Dump in the log memory controller configuration as read from the memory * controller registers. @@ -43,7 +50,7 @@ static void report_memory_config(void) const u32 ch_conf = MCHBAR32(MAD_DIMM(i)); printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf); - + printk(BIOS_DEBUG, " ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]); printk(BIOS_DEBUG, " enhanced interleave mode %s\n", ((ch_conf >> 22) & 1) ? "on" : "off"); |