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authorChristian Walter <christian.walter@9elements.com>2019-12-18 15:07:59 +0100
committerNico Huber <nico.h@gmx.de>2020-03-23 16:54:58 +0000
commitbe3979c873d23cb0543e635bba59bd85ab67fed0 (patch)
treec8a1064696607573eebd0b03c411a8aa090f015c /src/soc/intel/broadwell
parent09eb8d0c9b3b9e7b765520114d148a19926ff886 (diff)
downloadcoreboot-be3979c873d23cb0543e635bba59bd85ab67fed0.tar.xz
acpi: Change Processor ACPI Name (Intel only)
The ACPI Spec 2.0 states, that Processor declarations should be made within the ACPI namespace \_SB and not \_PR anymore. \_PR is deprecated and is removed here for Intel CPUs only. Tested on: * X11SSH (Kabylake) * CFL Platform * Asus P8Z77-V LX2 and Windows 10 FWTS does not return FAIL anymore on ACPI tests Tested-by: Angel Pons <th3fanbus@gmail.com> Change-Id: Ib101ed718f90f9056d2ecbc31b13b749ed1fc438 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel/broadwell')
-rw-r--r--src/soc/intel/broadwell/acpi.c2
-rw-r--r--src/soc/intel/broadwell/acpi/ctdp.asl6
2 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c
index 61f1008aa1..1664fdffef 100644
--- a/src/soc/intel/broadwell/acpi.c
+++ b/src/soc/intel/broadwell/acpi.c
@@ -517,7 +517,7 @@ void generate_cpu_entries(struct device *device)
plen = 0;
}
- /* Generate processor \_PR.CPUx */
+ /* Generate processor \_SB.CPUx */
acpigen_write_processor(
(cpuID - 1) * cores_per_package+coreID - 1,
pcontrol_blk, plen);
diff --git a/src/soc/intel/broadwell/acpi/ctdp.asl b/src/soc/intel/broadwell/acpi/ctdp.asl
index 86ebdd57da..6f3cad6d85 100644
--- a/src/soc/intel/broadwell/acpi/ctdp.asl
+++ b/src/soc/intel/broadwell/acpi/ctdp.asl
@@ -71,16 +71,16 @@ Scope (\_SB.PCI0.MCHC)
* Package (6) { freq, power, tlat, blat, control, status }
* }
*/
- External (\_PR.CP00._PSS)
+ External (\_SB.CP00._PSS)
Method (PSSS, 1, NotSerialized)
{
Store (One, Local0) /* Start at P1 */
- Store (SizeOf (\_PR.CP00._PSS), Local1)
+ Store (SizeOf (\_SB.CP00._PSS), Local1)
While (LLess (Local0, Local1)) {
/* Store _PSS entry Control value to Local2 */
ShiftRight (DeRefOf (Index (DeRefOf (Index
- (\_PR.CP00._PSS, Local0)), 4)), 8, Local2)
+ (\_SB.CP00._PSS, Local0)), 4)), 8, Local2)
If (LEqual (Local2, Arg0)) {
Return (Subtract (Local0, 1))
}