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authorStefan Reinauer <stefan.reinauer@coreboot.org>2015-07-07 00:54:05 +0200
committerStefan Reinauer <stefan.reinauer@coreboot.org>2015-07-07 18:30:55 +0200
commit4a45ec43fe73080517fa6f7cad6fa682ad49ecc4 (patch)
tree16f852f7658d8d079e34e556b86a13c5f687ad63 /src/soc/intel/broadwell
parentcfa9b99b23702ed35d61c9fcf3ad30ec55280174 (diff)
downloadcoreboot-4a45ec43fe73080517fa6f7cad6fa682ad49ecc4.tar.xz
x86: Drop -Wa,--divide
Fix up all the code that is using / to use >> for divisions instead. Change-Id: I8a6deb0aa090e0df71d90a5509c911b295833cea Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10819 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/broadwell')
-rw-r--r--src/soc/intel/broadwell/romstage/cache_as_ram.inc4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/broadwell/romstage/cache_as_ram.inc b/src/soc/intel/broadwell/romstage/cache_as_ram.inc
index ba90c25c72..05d4889f3f 100644
--- a/src/soc/intel/broadwell/romstage/cache_as_ram.inc
+++ b/src/soc/intel/broadwell/romstage/cache_as_ram.inc
@@ -63,7 +63,7 @@ wait_for_sipi:
post_code(0x21)
/* Zero out all fixed range and variable range MTRRs. */
movl $mtrr_table, %esi
- movl $((mtrr_table_end - mtrr_table) / 2), %edi
+ movl $((mtrr_table_end - mtrr_table) >> 1), %edi
xorl %eax, %eax
xorl %edx, %edx
clear_mtrrs:
@@ -119,7 +119,7 @@ clear_mtrrs:
/* Clear the cache memory region. This will also fill up the cache */
movl $CACHE_AS_RAM_BASE, %esi
movl %esi, %edi
- movl $(CACHE_AS_RAM_SIZE / 4), %ecx
+ movl $(CACHE_AS_RAM_SIZE >> 2), %ecx
xorl %eax, %eax
rep stosl