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authorMartin Roth <martinroth@google.com>2017-06-03 20:03:18 -0600
committerPatrick Georgi <pgeorgi@google.com>2017-06-07 12:09:15 +0200
commite18e6427d0f3261f9ec361d4418b8fe1dd7cc469 (patch)
treef6a10fc93dddada7e49108a5ad06e71590f2d54c /src/soc/intel/broadwell
parente81ce0483db982c741eebdda649111eee22a853b (diff)
downloadcoreboot-e18e6427d0f3261f9ec361d4418b8fe1dd7cc469.tar.xz
src: change coreboot to lowercase
The word 'coreboot' should always be written in lowercase, even at the start of a sentence. Change-Id: I7945ddb988262e7483da4e623cedf972380e65a2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/broadwell')
-rw-r--r--src/soc/intel/broadwell/acpi/globalnvs.asl2
-rw-r--r--src/soc/intel/broadwell/include/soc/nvs.h2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/broadwell/acpi/globalnvs.asl b/src/soc/intel/broadwell/acpi/globalnvs.asl
index fcc80d4460..b3b3a4f0c0 100644
--- a/src/soc/intel/broadwell/acpi/globalnvs.asl
+++ b/src/soc/intel/broadwell/acpi/globalnvs.asl
@@ -55,7 +55,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
LIDS, 8, // 0x16 - LID State
PWRS, 8, // 0x17 - AC Power State
CMEM, 32, // 0x18 - 0x1b - CBMEM TOC
- CBMC, 32, // 0x1c - 0x1f - Coreboot Memory Console
+ CBMC, 32, // 0x1c - 0x1f - coreboot Memory Console
PM1I, 64, // 0x20 - 0x27 - PM1 wake status bit
GPEI, 64, // 0x28 - 0x2f - GPE wake status bit
diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/soc/intel/broadwell/include/soc/nvs.h
index 202c56ae2f..55d6c8b4ea 100644
--- a/src/soc/intel/broadwell/include/soc/nvs.h
+++ b/src/soc/intel/broadwell/include/soc/nvs.h
@@ -46,7 +46,7 @@ typedef struct {
u8 lids; /* 0x16 - LID State */
u8 pwrs; /* 0x17 - AC Power State */
u32 cmem; /* 0x18 - 0x1b - CBMEM TOC */
- u32 cbmc; /* 0x1c - 0x1f - Coreboot Memory Console */
+ u32 cbmc; /* 0x1c - 0x1f - coreboot Memory Console */
u64 pm1i; /* 0x20 - 0x27 - PM1 wake status bit */
u64 gpei; /* 0x28 - 0x2f - GPE wake status bit */
u8 unused[208];