summaryrefslogtreecommitdiff
path: root/src/soc/intel/cannonlake/Kconfig
diff options
context:
space:
mode:
authorLijian Zhao <lijian.zhao@intel.com>2019-04-22 21:17:58 +0000
committerDuncan Laurie <dlaurie@chromium.org>2019-04-22 21:35:45 +0000
commit7f1a0e6b4c6a319d3cd552c708195d94b99bbb97 (patch)
tree799d6ed0f6794555f094f1d7d8dec6a059fe027a /src/soc/intel/cannonlake/Kconfig
parent69eae2762fc34f8303e8a41065df437295262586 (diff)
downloadcoreboot-7f1a0e6b4c6a319d3cd552c708195d94b99bbb97.tar.xz
Revert "soc/intel/cannonlake: Enable coreboot MP PPI service for WHL/CML"
This reverts commit 41dad286d846819242a84fc65faed2bbb35845ac. The change will make s0ix fail on Sarien/Arcada Platform. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I169bc6f41fba82fcf515267e8e1d08aa5ee2dce4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32391 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake/Kconfig')
-rw-r--r--src/soc/intel/cannonlake/Kconfig8
1 files changed, 0 insertions, 8 deletions
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 026aaf20ff..40b40d65ad 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -27,8 +27,6 @@ config SOC_INTEL_WHISKEYLAKE
bool
default n
select SOC_INTEL_COMMON_CANNONLAKE_BASE
- select FSP_PEIM_TO_PEIM_INTERFACE
- select USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI
help
Intel Whiskeylake support
@@ -36,12 +34,6 @@ config SOC_INTEL_COMETLAKE
bool
default n
select SOC_INTEL_COMMON_CANNONLAKE_BASE
- # TODO:
- # Delete FSP_PEIM_TO_PEIM_INTERFACE and
- # USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI selection
- # and select PLATFORM_USES_FSP2_1 once FSP support for CML is ready
- select FSP_PEIM_TO_PEIM_INTERFACE
- select USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI
help
Intel Cometlake support