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authorLijian Zhao <lijian.zhao@intel.com>2017-12-15 12:58:07 -0800
committerMartin Roth <martinroth@google.com>2018-01-05 20:44:15 +0000
commit031020e431f8d013108957b856da5ff5c7c596f3 (patch)
tree59c31103dcb0ce1a0580840c4e6c9332b15abaaa /src/soc/intel/cannonlake/Kconfig
parentd6f3dd83dc7d8bb66e29c489e82d4736779d7b6f (diff)
downloadcoreboot-031020e431f8d013108957b856da5ff5c7c596f3.tar.xz
soc/intel/cannonlake: Correct PMC/GPIO routing information
PMC and GPIO DWx definition is not identical, hence update that to correct information. For cannonlake lp PCH, GPIO group C, group E and group GPD is different for PMC GPIO_CFG and GPIO MISCCFG. Also add function call to set up GPE routing in bootblock stage. TEST=Boot up into OS, and manually check PMC GPE status Change-Id: I1edb83edabc72e8a762b129cf51dcd936cd37ddf Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Diffstat (limited to 'src/soc/intel/cannonlake/Kconfig')
-rw-r--r--src/soc/intel/cannonlake/Kconfig2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 51cd23fc47..a19a371374 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -165,7 +165,7 @@ config VBOOT
config C_ENV_BOOTBLOCK_SIZE
hex
- default 0x4000
+ default 0x8000
config STACK_SIZE
hex