diff options
| author | Nick Vaccaro <nvaccaro@chromium.org> | 2017-12-22 22:50:57 -0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-01-07 18:45:46 +0000 |
| commit | 780a1c44e190427522ee27e887b2a9ab692eb594 (patch) | |
| tree | 6052cb7faf581fe4186aa558c254f0a7f6191736 /src/soc/intel/cannonlake/Kconfig | |
| parent | a98727849ad06dd5464c88d485f57f09e090f5c4 (diff) | |
| download | coreboot-780a1c44e190427522ee27e887b2a9ab692eb594.tar.xz | |
soc/intel/cannonlake: provide LPDDR4 memory init
Instead of having the mainboards duplicate logic surrounding
LPDDR4 initialization provide helpers to do the heavy lifting.
It also handles the quirks of the FSP configuration which allows
the mainboard porting to focus on the schematic/design.
BUG=b:64395641
BRANCH=None
TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a"
compiles successfully.
Change-Id: I4a43ea121e663b866eaca3930eca61f30bb52834
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://review.coreboot.org/22204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/cannonlake/Kconfig')
| -rw-r--r-- | src/soc/intel/cannonlake/Kconfig | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index a19a371374..715cdf4ebb 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -131,6 +131,10 @@ config CPU_BCLK_MHZ int default 100 +config SOC_INTEL_CANNONLAKE_LPDDR4_INIT + bool + default n + config SOC_INTEL_COMMON_LPSS_CLOCK_MHZ int default 120 |