diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2017-10-10 18:26:18 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-10-18 17:52:11 +0000 |
| commit | 6cf501c3ae0278092cb76ccab015ad891af1fd48 (patch) | |
| tree | 4e50e2379607bc2c4a6211a63f15797637fef184 /src/soc/intel/cannonlake/Makefile.inc | |
| parent | 53660ed499fa2a523de4d7619fd1067f64f564fb (diff) | |
| download | coreboot-6cf501c3ae0278092cb76ccab015ad891af1fd48.tar.xz | |
soc/intel/cannonlake: Add finalize function
Before OS boot up, the following actions need to be taken.
1. Lock down PMC/SPI/DMI/TCO register.
2. Disable Sideband Access.
3. Disable Heci interface.
4. Disable PMtimer base on config settings.
TEST=Boot up into OS properly on both cannonlake y and cannonlake u rvp
board.
Change-Id: Icfa05b50fd76fbaeb856d398918990aedac4c5e6
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21943
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake/Makefile.inc')
| -rw-r--r-- | src/soc/intel/cannonlake/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 6fcee31adb..1076e10efe 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -30,6 +30,7 @@ romstage-$(CONFIG_UART_DEBUG) += uart.c ramstage-y += acpi.c ramstage-y += chip.c ramstage-y += cpu.c +ramstage-y += finalize.c ramstage-y += gpio.c ramstage-y += gspi.c ramstage-y += gpio.c |