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| author | Martin Roth <martinroth@google.com> | 2017-07-21 17:09:41 +0000 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-07-21 17:32:07 +0000 |
| commit | 70de396958627680a16992fbb8c5e6652dd35bf4 (patch) | |
| tree | 65031371771c45dc24241788b3958ecc66d2b611 /src/soc/intel/cannonlake/Makefile.inc | |
| parent | b137c13e57c667db861abc57dffe079ceaeea8c1 (diff) | |
| download | coreboot-70de396958627680a16992fbb8c5e6652dd35bf4.tar.xz | |
Revert "soc/intel/cannonlake: Call into FSP siliconinit"
This reverts commit dbe7f893c0e3fffc4e9862d872d65df752feaf9d.
This was merged too early. I'll repost it.
Change-Id: Ife56f45e91c0b961d0fad0e1872c6df3f9e18973
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20685
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake/Makefile.inc')
| -rw-r--r-- | src/soc/intel/cannonlake/Makefile.inc | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index f166f1a3fc..e427f98929 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -16,8 +16,7 @@ romstage-y += cbmem.c romstage-y += reset.c romstage-$(CONFIG_UART_DEBUG) += uart.c -ramstage-y += chip.c -ramstage-y += memmap.c +ramstage-y += cbmem.c ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c ramstage-$(CONFIG_UART_DEBUG) += uart.c |